ECE 551 -- Designing Application-Specific Integrated Circuits
ECE 551 (Section# 48023). Tues/Thurs 12:40 p.m. - 1:55 p.m. in 510 Ferris Hall
Don Bouldin, Ph.D.
Prof. of Electrical and Computer Engineering
419 Ferris Hall
1508 Middle Drive
University of Tennessee
Knoxville, TN 37996-2100
FPGA & ASIC Synthesis
This project-oriented course will present an overview of the
design of field-programmable gate arrays (FPGAs)
and application-specific integrated circuits (ASICs). Each
pair of students will capture a design using a
hardware description language (VHDL) and then use synthesis and automatic placement and routing software
to implement the design using multiple technologies (Altera and Xilinx).
LINUX workstations will be used extensively.
Goals of ECE 551:
To present an overview of FPGAs and ASICs that are suitable for tasks
which cannot be executed
efficiently by a general-purpose microprocessor.
To illustrate capturing a design in a technology-independent
means using a mix of levels (behavior and structure)
and then to map the synthesized result into several technologies which
can be compared.
To provide an in-depth project using FPGAs
that will involve architectural tradeoffs and simulation.
To reinforce the lectures and discussions with experience
using computer-aided design tools.
To develop human communication skills via a team project
requiring both written and oral reports.
What's New ?
Accessing a Remote Host (Putty & Xming)
Our New Text for $99 (John Wiley)
Author's Companion Site for Our New Text
Our Old Text On-Line for Free
Course Overview (pdf file)
Overview Slides (color pdf)
Overview Slides (handout b/w pdf)
Synthesizing Microelectronic Systems (197 KByte pdf)
Homework_1 - LOGIN, EMAIL and WEB PAGE
Homework 2 --
Homework 3 --
Using the Spartan3 Demo Board and Xilinx ISE Software
Homework 4 --
Animating Logic Simulations
Homework 5 -- Graphics <---> HDL
Homework_6 -- Targeting Xilinx and Altera; Using Asserts; Coverage
Homework_7 -- FPGA Design Using Graphical Tools
Project Checkoff Appts
VHDL Examples (our text)
VHDL Tutorial Examples