Tuesdays and Thursdays 8:10-9:25 AM

COSC530 covers the design and analysis of computer architecutres.

It offers an exploration of the central issues in computer architecture: instruction set principles and design, memory hierarchies (cache and main memories, mass storage, virtual memory) and design, pipelining, instruction-level parallelism, bus organization, RISC (Reduced Instruction Set Computers), CISC (Complex Instruction Set Computers), multiprocessors, implementation issues, technology trends, architecture modeling and simulation. Recommended Background: Course work in architecture or machine organization.

Some familiarity with discrete mathematics (CS311 or equivalent). This background should include a working knowledge of counting and probability theory, and simple proofs by mathematical induction.

*Computer Architecture: A Quantitative Approach*, 5th Edition by John Hennessy and David Patterson, Publisher: Morgan Kaufmann

- Exam 1 — 20%
- Exam 2 — 20%
- Exam 3 (cumulative) — 40%
- Homework (~bi-weekly) — 10%
- Project — 10%

- Chapter 1: Fundamentals of Quantitative Design and Analysis
- Chapter 2: Memory Hierarchy Design
- Chapter 3: Instruction Level Parallelism and Its Exploitation
- Chapter 4: Data-Level Parallelism in Vector, SIMD, and GPU Architectures
- Chapter 5: Thread-Level Parallelism
- Chapter 6: Warehouse-Scale Computers to Exploit Request-Level and Data-Level Parallelism
- Final Review

- Homework 1: due September 17, 2013
- Textbook problem 1.5 (page 63)
- Textbook problem 1.7 (page 64)
- Textbook problem 1.9 (page 65)
- Textbook problem 1.13 (page 66)
- Textbook problem 1.14 (page 66)
- Textbook problem 1.18 (page 68)

- Homework 2: due October 22, 2013
- Textbook problem C.1 (page C-82)
- Textbook problem C.4 (page C-84)
- Textbook problem C.12 (page C-86) only part (a)
- Textbook problem C.14 (page C-88)
- Textbook problem C.14 (page C-88) additional parts
- Part (c) Demonstrate a WAR hazard requiring a stall
- Part (d) Demonstrate a RAW hazard requiring a stall

- Homework 3: due November 26, 2013
- Textbook problem C.12 (page C-86) only part (b)
- Textbook problem 5.1 (page 412)
- Textbook problem 6.14 (page 480) only part (a), (b), (c) but not (d)

- Exam 1
- Date: September 24, 2013
- Scope: Chapters 1, 2 (and Appendices A and B)
- Closed book
- Study guide with a sample problem from textbook's Appendix B. (study guide's LaTeX source)
- Score statistics:
- Minimum: 50
- Harmonic Average: 72.78
- Geometric Average: 74.92
- Median: 75.5
- Arithmetic Average: 77.10
- Maximum: 110
- Standard deviation: 18.79
- Variance: 352.94

- Exam 2
- Date: October 31, 2013
- Scope: Chapters 3, 4 (and Appendices C, G and H)
- Closed book, no cell phones, no computers, no notes
- Exam 2 Study Guide PDF (Exam 2 Study Guide OpenDocument)
- Score statistics:
- Minimum: 80%
- Average: 92%
- Maximum: 100%

- Projects are done in groups of 4-5
- Projects topics and group assignments are due November 5
- Suggested topics and ideas for projects
- Deep dive into a specific computer architecture (4 generations of Intel Core, AMD Opterons, ARM Cortex-A*, Chinese MIPS (and non-MIPS) processors, GPUs and coprocessors: similarities and differences)
- Deep dive into specific system components: disks (RPMs, densities, RAID, past developments and future trends), interconnects (on-chip, in-rack, LAN, WAN), solid state media (specs, quality, dependability)
- Historical perspectives on computer architecture and design: 6+ decades of Moore's Law, Dennard's Law, Amdahl Law, Gustafson Law, ...
- Paradigm shifts in computer architecture: power consumption and dissipation, problems with feature size decreases, consolidation of global chip industry, ...
- Programming: optimization exercise for a real-world (non-trivial) application that uses techniques studied in class and shows what works and what doesn't, benchmarking of interesting system parameters and hardware
- Emerging technologies: Non-Volatile and other types of RAM, Near-Threashold Voltage computing, ...

- Other topics are welcome as long as their relevant to the class material: please consult with me early.
- Group members and project topics are due November 19 or earlier (email)
- Lectures on November 19 and 21 are devoted partially to work on projects
- Projects' written part is handed in on December 3 and is followed by a 15 minute presentation during lecture on December 3

- 8:10-8:25 IBM Cell Processor (IBM CELL presentation and IBM CELL report)
- 8:25-8:40 Cache simulator (cache simulator Python source code)
- 8:40-8:55 Intel Core architecture (Intel Core presentation and Intel Core report)
- 8:55-9:10 Dalvik VM vs. Java VM (Dalvik report)
- 9:10-9:25 Arm Cortex-A* architecture (ARM Cortex presentation and ARM Cortex report)

*Office:*Claxton 316*Email:*`luszczek at eecs.utk.edu`

*Office Hours:*please send email for appointment, or stop by to chat from 8 to 5 weekdays.

**TA:** Rui Ma

*Email:*`rma at utk.edu`

*Office:*MinKao RM349*Office hours:*Tuesdays and Thursdays 12:30-5:30 (or by appointnemt)

- Chapter 1: August 22, 27, 29
- Chapter 2: September 3, 5, 10 (guest lecturer), 12 (guest lecturer)
- Chapter 3: September 17, 19
- Chapter 3: September 26; October 1
- Chapter 4: October 3, 8, 10, 15
- Chapter 5: October 22, 24, 29; November 5
- Chapter 6: November 7, 12, 14
- Homework 1: September 5 (Chapter 1 material)
- Homework 2: October 1 (Chapter 3 and 4 material)
- Homework 3: November 7 (Chapter 5 and 6 material)
- Exam 1: September 24
- Exam 2: October 31
- Exam 3: December 12 (8am-10am)

Last updated: December 12, 2013 (Summary of changes)