#include <msp430.h> 


/**
 * main.c
 */
int main(void)
{
	WDTCTL = WDTPW | WDTHOLD;	// stop watchdog timer
	
    // Disable the GPIO power-on default high-impedance mode
    PM5CTL0 &= ~LOCKLPM5; //For MSP430FR5994 device

    // Configure one FRAM waitstate as required by the device datasheet for MCLK
    // operation beyond 8MHz _before_ configuring the clock system.
    FRCTL0 = FRCTLPW | NWAITS_1;


    //Set P3.4 and P3.5 to outputs
    //P3DIR = 0b00110000;  //Also clears all other bits, making P3.7-3.6 & P3.3-3.0 to inputs
    //P3DIR |= 0b00110000; //OR-equals, only sets P3.4 and P3.5 to outputs, other bits are untouched
    P3DIR |= BIT4 + BIT5; //Same, using predefined constants from header file

    P3OUT |= BIT4; // Set P3.4 High
    P3OUT &= ~BIT5; // Set P3.5 Low

    P3SEL0 |= BIT4 + BIT5; //Set pin 3.4 & 3.5 to Primary module function (TB0.3 & TB0.4)

    //Set CPU clock to 24 MHz
    CSCTL0_H = CSKEY_H; //Unlock Clock System Registers
    CSCTL3 = DIVA__4 + DIVS__4 + DIVM__4; // set clock dividers to 4
    CSCTL1 = DCOFSEL_6 + DCORSEL; //Set DCO clock to 24 MHz
    CSCTL2 = SELA__VLOCLK + SELS__DCOCLK + SELM__DCOCLK; //Set MCLK and SMCLK to DCO, ACLK to VLO
    __delay_cycles(240);
    CSCTL3 = DIVA__1 + DIVS__1 + DIVM__1; // set clock dividers to 1
    CSCTL0_H = 0; //Re-lock Clock System Registers

    //Set TimerB0 to output a 240 kHz, 25% duty cycle pwm output
    TB0CTL = CNTL_2 + TBSSEL_2 + ID_0 + MC_1 + TBCLR + TBIE;
    TB0CCR0 = 100;

    TB0CCTL3 = OUTMOD_6;
    TB0CCR3 = 25;

    TB0CCTL4 = OUTMOD_2;
    TB0CCR4 = 25;
    while(1)
    {
        __bis_SR_register(LPM0_bits | GIE);
    }


	return 0;
}

// TimerB Interrupt Vector (TBIV) handler
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=TIMER0_B1_VECTOR
__interrupt void TIMER0_B1_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(TIMER0_B1_VECTOR))) TIMER0_B1_ISR (void)
#else
#error Compiler not supported!
#endif
{
    switch(__even_in_range(TB0IV, TBIV__TBIFG))
    {
        case TBIV__NONE:    break;          // No interrupt
        case TBIV__TBCCR1: break;           // TB0CCR1 interrupt
        case TBIV__TBCCR2: break;           // TB0CCR2 interrupt
        case TBIV__TBCCR3: break;           // TB0CCR3 interrupt
        case TBIV__TBCCR4: break;           // TB0CCR4 interrupt
        case TBIV__TBCCR5: break;           // TB0CCR5 interrupt
        case TBIV__TBCCR6: break;           // TB0CCR6 interrupt
        case TBIV__TBIFG:                   // overflow
            TB0CCR3 = TB0CCR3 + 1;
            if (TB0CCR3 > 99)
            {
                TB0CCR3 = 1;
            }
            break;
        default: break;
    }
}