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TITLE: MULTI-LEVEL SYNTHESIS FOR SOC
Synthesis of integrated circuits traditionally consists of
translating a VHDL or Verilog hardware description into a logic
net-list. Recently, multi-level synthesis has been introduced by
a start-up company, Get2Chip, in which a single tool combines
micro-architecture and register transfer language generation,
datapath and logic synthesis as well as floor planning. This
approach facilitates the development of multi-million gate
system-on-chip designs and enables designers to create, reuse,
exchange and integrate intellectual property (IP) blocks quickly.
For additional information, access: GET2CHIP
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