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TITLE: SYSTEM-ON-CHIP-IN-A-DAY METHODOLOGY
Prof. Bob Brodersen of the University of California, Berkeley, is
an advocate of a SoC (system-on-chip)-in-a-day methodology.
During his keynote address at the Microelectronic Systems Educa-
tion Conference this summer, Prof. Brodersen described the
Berkeley Wireless Research Center (BWRC) and their approach to
developing next generation wireless communication devices which
have RF, analog and digital processing functions on a single
integrated circuit. In this domain, two figures of merit are
important: energy efficiency and cost or area efficiency. He
defined energy efficiency as arithmetic operations (multiply,
add, etc.) per second per watt and area efficiency as arithmetic
operations per second per square millimeter. Using these figures
of merit, general-purpose CPUs are a factor of 100 to 1000 worse
than a SoC that has a carefully controlled layout. He attributes
this disparity to the Von Neumann architecture employed in the
CPU which time-shares the silicon or hardware. However, in
today's world of integrated circuity technology, silicon or
hardware is cheap since thousands of multipliers can be placed on
a single IC. Using 0.13-micron CMOS, 8000 multipliers (16-bit x
16-bit) can be included on a single SoC since one of these
consumes only 0.01 sq. mm. of silicon. This leads Prof.
Brodersen to advocate the use of parallelism, not by placing
multiple Von Neumann CPUs together, but instead by employing
multiple arithmetic units on a single SoC. To achieve this type
of parallelism, his researchers are describing their applications
using Simulink, a graphical entry system which has
implicit parallelism. The new design methodology differs from
traditional ASIC design flow in that it does not describe the
application parallelism using a sequential language like C and
then try to rediscover the parallelism during synthesis but
instead preserves the parallelism of the original application
description and maps the arithmetic units directly into the
layout in accordance with a domain-specific floorplan. Using
this type of IC design flow, a scripted path from Simulink to
layout has been fully automated, can be executed in less than a
day, and produces ICs that have predicatable delays and hence
timing closure. Papers and presentations describing this new
methodology are on the BWRC website listed above.
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FILENUMBER: 1012
BEGIN_KEYWORDS
SYSTEM-ON-CHIP-IN-A-DAY METHODOLOGY
END_KEYWORDS
DATE: July 2001
TITLE: SYSTEM-ON-CHIP-IN-A-DAY METHODOLOGY
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