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TITLE: DESIGNING RADIATION-TOLERANT INTEGRATED CIRCUITS
High-radiation environments occur in space and military systems
as well as nuclear particle physics accelerators. Radiation in
space may result from particles trapped in planetary magnetic
fields, cosmic rays, or high-energy protons from solar events. At
low Earth orbit, an integrated circuit may be exposed to a few
kilorads of radiation over its useful lifetime. In addition to
the natural space environment, military satellites must be able
to survive transient bursts of radiation resulting from a hostile
nuclear explosion. To achieve these higher levels, radiation-
hardened integrated circuits are required. In general, these
circuits are fabricated using specialized processes and designs
that increase their tolerance to ionizing radiation by several
orders of magnitude. [1]
The primary effects of natural space radiation on spacecraft
electronics are total ionizing dose (TID) and single event
effects (SEE). TID creates bulk-oxide and an interface-trap
charge that reduces transistor gain and shifts the operating
properties (e.g., threshold voltage) of semiconductor devices.
TID accumulation will cause a device to fail if (1) the
transistor threshold voltage shifts far enough to cause a circuit
malfunction, (2) the device fails to operate at the required
frequency, and/or (3) electrical isolation between devices is
lost.
Figure 1 illustrates the desired current-voltage behavior of an
MOSFET as well as the change that may occur due to radiation
effects. [2]
To counter this situation, one technique is to adjust the
conventional integrated circuit fabrication process to form a
"guardband" using ion implantation. Adding this step effectively
shuts off radiation-induced parasitic leakage paths. For improved
latchup and transient immunity, the change can sometimes be as
simple as use of a thin epitaxial substrate. SOI technology that
employs an active device layer built on an insulating substrate
can (with proper design) provide significant improvement in SEE
and transient tolerance.
However, changing a fabrication process may involve significant
additional expense but there are design approaches that can be
used to increase radiation hardness. For SEU, memory cells with
additional transistors can provide redundancy and error-
correction coding (ECC) to identify and correct errors. For TID,
n-channel transistors can be designed in "closed" geometry that
shuts off parasitic leakage paths as shown in Figure 1b. Thus, a
high degree of radition tolerance can be achieved without the
expense of modifying the conventional CMOS fabrication process.
Commercial CMOS circuits are typically able to withstand TID
levels in the range from 5 to 30 kilorads and have been used in
spacecraft that are placed in low Earth orbit where the
electronics may be exposed to only a few kilorads of TID during
its lifetime. Scientists and engineers and NASA's Goddard Space
Flight Center perform testing and analysis of commercial products
to determine radiation effects on their operation. An extensive
set of results are published on their website.
Also, several papers are presented on this subject each year at
the Military and Aerospace Applications of Programmable Logic
Devices (MAPLD). For archived papers and presentations as well
as information about the next conference, access: MAPLD.
CMOS circuits are generally the least sensitive to SEU due to the
presence of active devices which restore the original voltage
level of a node following a voltage transient induced by a
heavy-ion strike. Combined with their low power requirements,
CMOS circuits are often the choice for space applications. Still,
unhardened CMOS SRAMs may experience upsets at a rate of 10-5 to
10-3 errors/(bit-day), which represents an upset every hour for a
satellite with a large memory element in low-Earth orbit that
passes through the South Atlantic Anomaly, an area of
exceptionally high proton density that overlies much of South
America and the South Atlantic Ocean.
Dynamic circuits are generally very sensitive to SEU and are not
used in critical space applications. In dynamic circuits, such as
DRAMs (dynamic random access memories) and CCDs (charge coupled
devices), information is represented as charge stored on a
circuit node. In DRAMs this charge gradually leaks off the
storage node and must be refreshed periodically. Upset in these
devices occurs if sufficient charge is collected at a struck node
to compensate the original stored charge. Although DRAMs and CCDs
are not recommended for critical circuit applications, they have
found increasing use in solid state data recorders and imaging
systems where robust ECC can restore corrupted data.
[1] P. Winokur, "Why Semiconductors must be hardened for space
deployment", IEEE Nuclear Plasma and Sciences Society News, No.
2, June, 2000.
[2] G. Anelli et al., "Radiation Tolerant VLSI Circuits in
Standard Deep Submicron CMOS Technologies for the LHC
Experiments: Practical Design Aspects", IEEE Transactions on
Nuclear Science, vol. 46, no. 6, December 1999, pp. 1690-1696.
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FILENUMBER: 1040
BEGIN_KEYWORDS
DESIGNING RADIATION-TOLERANT INTEGRATED CIRCUITS
END_KEYWORDS
DATE: February 2002
TITLE: DESIGNING RADIATION-TOLERANT INTEGRATED CIRCUITS
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