=================================================================
TITLE: CHIP INDUSTRY TACKLES ESCALATING MASK COSTS
By Ron Wilson, EE Times
Jun 17, 2002
EE TIMES -- June 17, 2002
The rapid increase in the cost of photomask sets for advanced IC
processes has made a lot of news in recent months. When word got
around that a mask set for leading-edge 130-nanometer processes
could cost more than $1 million and for 90-nm processes, $2
million, the semiconductor industry went into a collective state
of shock. But behind the scenes forces are converging on the
problem with a variety of solutions.
Perhaps the most obvious, given the huge number of transistors
that can be fit into the real estate covered by a reticle, is to
share the masks. The technique, commonly referred to as
multiproject wafers, has been used as a means of prototyping and
to provide limited runs for university projects for years. The
acknowledged leader in this area has been a relatively low-
profile not-for-profit organization, the MOSIS Service.
Originally funded by the Defense Advanced Research Projects
Agency, MOSIS was conceived in the early 1980s to give
researchers subsidized access to a foundry. Cut loose from DARPA
funding in 1994, the organization still serves universities and
research centers. But it is also emerging as an important access
point into the foundry industry for commercial ventures needing
test chips, prototype runs or increasingly moderate production
runs at sharply reduced mask costs.
Working closely with both clients and foundries including Taiwan
Semiconductor Manufacturing Co. and IBM Microelectronics, MOSIS
packs a number of client designs into a single mask set and then
has the wafers processed at the appropriate fabrication facility.
The company now can return anything from wafers to dice to fully
packaged ICs from the run. The service is available for anything
from a run of 40 test chips to a few thousand production ICs.
Available processes include TSMC's 180-, 250- and 350-nm CMOS
logic and mixed-signal processes, and IBM's 250- and 500-nm
silicon germanium BiCMOS processes, among others.
The addition of SiGe means a new relationship between MOSIS and
its clients, said deputy director Wes Hansford. "A lot of our
growth now is coming from commercial design teams exploring their
technology options," he said. "They may want to compare what can
be done in CMOS and SiGe, for example, and we give them an
affordable way to actually build chips in each process and
compare them."
Hansford said that the service is also being used to manage the
perceived risks involved in new circuit development, particularly
with mixed-signal designs. A design team may create a set of test
patterns intended only for cell characterization. Or it may tape
out an entire functional block of its intended system-on-chip
(SoC) to examine not only the parametric characteristics of the
devices, but the overall functional behavior. Either way, the die
area involved is quite small, and the mask cost for a
conventional run would be prohibitive.
Even using the foundries' existing prototype services, such as
TSMC's CyberShuttle, can present a problem for such small
objects. For example, CyberShuttle divides the maximum reticle
area into fixed regions, and the user has to pay for some integer
number of regions. MOSIS, in contrast, hand-packs the designs
into the reticle, so it does not have any fixed size or aspect
ratio requirements, said Hansford.
Although characterization and prototyping are the conventional
uses of the service, Hansford said that there is also a growing
use of MOSIS as a production shop. With a minimum run of even
200-mm wafers in 180 nm yielding a huge number of dice, many
designs may never reach what TSMC would regard as production. So
the ability to slip a job into the multiproject wafer flow and
pull out a few thousand dice can be a design team's only access
to advanced processes.
While MOSIS slashes mask costs by sharing mask sets, the mask
vendors themselves are addressing the issue of spiraling cost in
a different way: education. "Traditionally, design teams just did
their design, ran the design rule checks and if everything
passed, they pitched the thing over the wall to the mask shop.
They didn't know or care what happened next," said Dan Del
Rosario, chief executive officer of Photronics Inc. (Jupiter,
Fla.). "But in the region starting at about 130 nm, that needs to
change. There are significant decisions that the design team and
the foundry make that can substantially influence mask costs. And
those should not be transparent to the SoC designers."
The main issue, Del Rosario said, is that different mask layers
have different resolution requirements. Usually the poly, contact
and active-area masks will have the finest features. Masks for
the upper metal layers can be comparatively crude.
In larger geometries, when even the most detailed masks still had
feature sizes near the wavelength of the stepper light source,
all the masks could be produced on the same equipment using the
same technology. But now, the critical-layer masks require the
most expensive and slow equipment and demand the most difficult
techniques. "There are now three categories of masks," Del
Rosario said. "Out of a set of 32, about two-thirds will be
noncritical and about a third will be critical. You can produce
those masks on scanning-laser equipment with pretty good
throughput. But two to three of the masks will be extremely
critical. They will require directed e-beam equipment. Now you
can be talking about 24 hours just to expose the mask on the e-
beam system.
"Much of the cost of the mask set depends on just how much you
demand of those critical masks. And that in turn depends on the
process often on details of the process that are not readily
visible to the design team."
For instance, Del Rosario said, a foundry may decide to save on
costs by using a 248-nm stepper instead of a state-of-the-art
193-nm one to do the poly. But that forces the mask shop to use
the most difficult available mask technology: hard phase
shifting. If the fab employs the 193-nm steppers, the mask shop
may be able to use aggressive optical proximity correction (OPC)
instead of hard phase shifts, at a considerable savings to the
design team.
"A typical binary mask using aggressive OPC may cost $20k," Del
Rosario said. Moderate phase-shift techniques using a halftone
mask cost $50,000. "If you require hard phase shifting, that's
going to cost you $130k. It makes a big difference."
The problem forces designers to consider issues about which they
have been blissfully indifferent. Choices of stepper, mask type
and writer type all interact with one another and with the design
rules, and those differences can show up in the range and
performance of library cells available to the designers. As
dimensions continue to shrink these choices will also have
consequences on yield and on long-term reliability. "Part of the
answer has to be an integration of the decision-making processes,
all the way from design through fabrication," Del Rosario said.
=================================================================
FILENUMBER: 1063
BEGIN_KEYWORDS
CHIP INDUSTRY MASK COSTS MOSIS
END_KEYWORDS
DATE: July 2002
TITLE: CHIP INDUSTRY TACKLES ESCALATING MASK COSTS
Return to MSN Home Page