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TITLE: MAPPING OPTIMUM WORD-LENGTH DSP ONTO FPGAS
An integrated algorithm analysis and mapping environment
for translating a dataflow representation of a signal
processing algorithm onto FPGAs has been developed by BAE
Systems under DARPA sponsorship. This environment allows
designers to transform signal processing algorithms an order
of magnitude faster than previously. The software is
available to others as part of the UC Berkeley Ptolemy project.
For many DSP problems, reduced precision arithmetic can
save area and power yet maintain acceptable system
performance. Designing optimal wordlength combinations for
dataflow graphs can be very difficult due to the exponential
number of wordlength combinations that must be considered.
Naive random sampling approaches are ineffective for large
flowgraphs because most of the samples do not correspond to
feasible or useful designs. In this research, a Markov Chain
Monte Carlo (MCMC) sampling approach is used to find good
wordlength combinations for DSP flowgraphs. A feasible region
of wordlengths is defined that consists of designs near the
Pareto-optimal cost/quality boundary which also satisfy any
feasibility constraints. The MCMC sampler is then used to
generate uniform samples from this feasible region.
An overview of the research may be found at: BAE Final Report.
Details about the word length optimization are presented in Paul
Fiore's Ph.D. Thesis.
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FILENUMBER: 1070
BEGIN_KEYWORDS
MAPPING OPTIMUM WORD-LENGTH DSP FPGAS
END_KEYWORDS
DATE: July 2002
TITLE: MAPPING OPTIMUM WORD-LENGTH DSP ONTO FPGAS
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