MICROELECTRONIC SYSTEMS NEWS
FILENUMBER: 1092
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SYSTEM-ON-CHIP DESIGN SIMULATION CO-VERIFICATION FORESIGHT
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DATE: November 2002
TITLE: SYSTEM-ON-CHIP DESIGN, SIMULATION AND CO-VERIFICATION
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TITLE: SYSTEM-ON-CHIP DESIGN, SIMULATION AND CO-VERIFICATION
Foresight-Systems, Inc. offers tools for system level modeling
and simulation that help designers identify and eliminate errors
early in the product development process. Thus, a system level
"executable specification" can be used to highlight performance
problems, inconsistent and/or conflicting requirements, and
an incomplete functional representation before actual
implementation begins. The tools have been used on hundreds of
complex embedded system designs ranging from large scale
systems applications such as the Joint Strike Fighter design and
the Mars Rover Project to complex system-on-chip designs for
imaging, multimedia, and telecommunications such as a digital
camera chip.
By mapping functional elements of a design to a variety of
alternative architectures, system designers can quickly explore
tradeoffs, allowing them to achieve an optimal specification. It
is then possible to replace high level architectural elements
with detailed hardware/software components emulated in Mentor
Graphics Corp's Seamless Co-Verification Environment
(Seamless CVE) and HDL simulation environment (ModelSim).
Foresight tools can also be used in conjunction with MATLAB.
For additional information, access: WWW
Foresight-Systems, Inc.
1430 Spring Hill Road, Suite 220
McLean, VA 22102
TEL: 703-356-5056
FAX: 703-356-0498
EMAIL: info@foresight-systems.com
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dbouldin@utk.edu
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