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TITLE: IC PLACEMENT TOOLS ARE NOT YET OPTIMAL
EE Times-Feb. 5, 2003
Current IC placement algorithms leave so much excess wire that
chip designs are essentially several technology generations
behind where they could be, according to a recent paper by
researchers at the University of California at Los Angeles
(UCLA). EDA vendors have responded by stating that commercial
placement tools are not as deficient as the study suggests. The
paper, "Optimality and scalability study of existing placement
algorithms," raised a stir when it was delivered last month at
the ASP-DAC conference in Japan. Using synthetic benchmarks
ranging from 10,000 to 2-million placeable modules, it evaluates
three academic placement algorithms along with the commercial
QPlace product from Cadence Design Systems Inc.
The results were "quite surprising," said co-author Jason Cong,
co-director of the VLSI CAD lab at UCLA. The paper concluded that
wire lengths resulting from the placement tools were an average
of 1.46 to 2.38 times longer than the optimal solution, and that
the wire utilization of the tools deteriorates an additional 4
percent to 25 percent when the size of a design increases by a
factor of ten. If the "optimality gap" in wire length could be
closed, Cong said, the benefits would be equivalent to advancing
several technology generations. "If you go from aluminum to
copper, you get the equivalent of a 30 percent wire length
reduction," he said. "If you go through one process of scaling,
you get a 30 percent reduction. If we can do this through
software optimization, the return on investment is huge."
UCLA
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