MICROELECTRONIC SYSTEMS NEWS

FILENUMBER: 1122 BEGIN_KEYWORDS ASIC TIMING OPTIMIZATION END_KEYWORDS DATE: May 2003 TITLE: ASIC Timing Optimization
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TITLE: ASIC Timing Optimization

A new EDA tool is now available to help ASIC design  teams  reach
their  targeted  performance  goals quicker and easier.  ZenTime,
which is offered by Zenasis Technologies, uses a unique hybrid of
transistor,  logic,  and physical optimization to generate timing
gains that are  2-4x  larger  than  conventional  timing  closure
tools.  In  a  130-nanometer process, ZenTime can reportedly gain
over 50 MHz in additional performance.  Timing closure tools that
simply  re-buffer  and re-size the critical paths can only affect
timing by small  amounts.  Physical  synthesis  greatly  improves
timing  accuracy  but  only  has a limited ability to improve the
actual timing. Global floorplanning helps minimize long-wires but
it's  a tricky, manual, non- deterministic process.  ZenTime uses
placement  accurate  timing  to  identify   timing   road-blocks,
transistor-level   optimization   to  break  the  road-blocks  by
crafting context-specific  cells  for  the  critical  logic,  and
physical   optimization  to  restructure  surrounding  logic  and
capitalize on  the  local  improvements.  By  optimizing  at  the
transistor-level,  the  tool  often  finds ways to improve timing
using fewer or smaller transistors and  fewer  inter-cell  wires.
The  crafted  cells inserted by the tool use the same cell layout
architecture as the standard  cell  library,  so  place-and-route
tools  see  no  difference between the standard cells and the new
crafted cells.

For additional information, access: ZENASIS

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