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TITLE: System-Verilog Enhances Model Verification
SystemVerilog is an extensive set of enhancements to the IEEE
1364 Verilog-2001 standard. These enhancements provide powerful
new capabilities for modeling hardware at the RTL and system
level, along with a rich set of new features for verifying model
functionality. As design sizes have increased during the past
few years, the number of lines of RTL code required to
represent the design have increased dramatically. Even more
significant is the increase in the amount of verification code
required to test these very large designs.
The SystemVerilog standard currently being defined by
Accellera, a non-profit consortium, incorporates high-level
modeling constructs from the Superlog language developed by
Co-Design, testbench constructs from the Open Vera language and
VCS DirectC interface technology from Synopsys. It also includes
assertions work of OVA from Verplex, ForSpec from Intel and Sugar
(now called PSL) from IBM. An assertion is a statement that a
specific condition, or sequence of conditions, in a design is
true. If the condition or sequence is not true, the assertion
statement will generate an error message. A SystemVerilog
assertion can test for a sequence of conditions that span
multiple clock cycles.
For additional information, access: ACCELLERA
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FILENUMBER: 1123
BEGIN_KEYWORDS
SYSTEM-VERILOG VERIFICATION
END_KEYWORDS
DATE: May 2003
TITLE: System-Verilog Enhances Model Verification
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