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TITLE: ASIC Trends
Increasing mask costs are reducing the number of ASIC design
starts and affecting the content and approach of ASIC designs.
According to a SemaTech report, a mask set for 130-nm logic
devices costs about $750,000, and projections indicate that a
90-nm mask set will cost $1.6 million. A mask set for 65-nm is
likely to cost $3 million. Moreover, ASIC masks have
traditionally been used to produce 1000 wafers, but with the
added complexity of deep submicron fabrication, about 15% of ASIC
designs require up to four respins. Thus, a large percentage of
masks are used for less than 100 wafers.
One strategy to help reduce costs associated with masks is to use
the multi-project approach supported for over twenty years by
silicon brokers such as MOSIS, CMP and Europractice. These
facilitators accept designs from multiple sources including low
volume commercial customers and universities. Foundries such as
TSMC also have multi-project runs but generally reserve these for
customers who are planning high volume production.
Direct-write or mask-less lithography is another approach being
pursued by some companies. However, the throughput of this
approach limits its cost-effectiveness.
The increasing expense of masks along with the decline in demands
for the telecommunications sector of the economy have led to a
50% reduction in ASIC design starts in the last five years and a
continued decline has been forecast.
Another strategy to counter the increasing cost of masks is the
development of programmable platforms which are manufactured in
high volume and then customized using software and firmware. An
example is the Virtex-II Pro offered by Xilinx which includes one
or more PowerPC cores plus logic, memory and interconnect that
can be configured by the user.
LSI Logic has introduced a family of pre-fabricated platforms
that can be customized using metal masks. Similar yet different
than the classical gate-array approach, the seven platforms each
contain hard cores and memory along with customizable logic
targeted to particular application domains. Most contain an ARM
processor and at least 500,000 customizable gates.
Other companies have developed "showcase" platforms (e.g.
Philip's Nexperia) in which multiple blocks have been reused or
integrated into a complete system-on-chip or system-in-package.
Application designers can customize the platforms with software
and firmware or derivative ASICs can be developed within a six-
month time frame instead of the traditional one to two years.
This approach is similar to that practiced by building
contractors who produce model homes to illustrate to potential
buyers their expertise and experience.
In some cases, companies offer reusable blocks or cores to
designers to incorporate into their own ASICs. These may be
synthesizable to maintain foundry flexibility or they may be hard
layouts which have been fully characterized in silicon and hence
present less risk to the user. Interconnect delay, cross-talk
and noise concerns inside large blocks have become increasingly
significant issues in deep submicron design so greater care over
physical design issues has taken place in the past few years.
ASIC platforms generally contain millions of transistors whose
energy must be carefully managed for reliability and packaging
reasons. Likewise, smaller ASICs targeting embedded system
applications that are portable are energy-sensitive.
Consequently, electronic design automation tools and techniques
are focusing on power-aware design. The use of just two levels
of power supply voltages and transistor thresholds has been shown
to reduce the total static and dynamic power consumption by one-
third or more. Using more than two levels generally exceeds the
point of diminishing return due to the area and power needed to
implement the required level shifters.
For additional information, access:
SemaTech
MOSIS
CMP
Europractice
Direct-Write
ASIC Starts
Xilinx
LSI Logic
Nexperia
Synopsys
Design Reuse
Power Aware Design
Physical Design
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FILENUMBER: 1126
BEGIN_KEYWORDS
ASIC Trends
END_KEYWORDS
DATE: July 2003
TITLE: ASIC Trends
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