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TITLE: Achieving 40x Reduction in Power with 0.5V CMOS
ASIC designers at the Center for Advanced Microelectronics and
Biomolecular Research, CAMBR, at the University of Idaho have
developed over 25 chips that have flown in space. The chips
perform a variety of high performance digital signal processing
tasks including error correction, data compression and
tranformation, and correlation. Since power is related to the
square of the applied voltage, ultra low-power circuits have been
designed with the power supply voltage less than one volt.
Specifically, logic and memory circuits which can operate with a
power supply voltage of 0.5 volts have been implemented with only
one additional implant being added to AMI Semiconductor's
standard 0.35-micron CMOS process. An adjustable back-bias
circuit was then used to keep the transistor threshold between
100-170 mV. Extreme care must be taken in the design of these
circuits to meet the specifications for performance and noise
immunity in light of process variations and temperature changes.
When compared to a conventional Reed-Solomon encoder operating
with a 3.3V power supply, the 0.5V implementation can achieve a
40x reduction in power. Furthermore, chips designed using these
techniques have experienced no latchup problems while improving
total dose tolerance up to 200 KRad.
For additional information, access:
CAMBR
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FILENUMBER: 1129
BEGIN_KEYWORDS
40x Reduction Power 0.5V CMOS
END_KEYWORDS
DATE: July 2003
TITLE: Achieving 40x Reduction in Power with 0.5V CMOS
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