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TITLE: Advanced IC Processes Being Developed By Intel
Intel presently manufactures its Pentium-4 processor in high-
volume production using a 90-nm CMOS process. However, new
high-k mails are being developed to provide dielectrics thinner
than silicon dioxide. Using just five atomic layers, high-k
insulation can be made a mere 1.2-nm thick. Making the
dielectric ever thinner is necessary in order to meet
increasing performance goals. When the gate dielectric of a
transistor thins, its insular quality decreases and current leaks
through it. Uncontrolled, this conduction causes the transistor
to stray from its purely "on" and "off" state and into an "on"
and "leaky off" behavior.
Intel announced recently that it has already built fully
functional SRAM chips using a 65-nm CMOS process and is on
track for high-volume production in 2005 using 300 mm wafers.
This new process combines higher-performance and lower-power
transistors with eight layers of copper interconnects and
low-k dielectrics so that Intel can double the number of
transistors it can build on a single chip today. Thus, Intel
expects to extend its 15-year record of ramping production on a
new process generation every two years. The 65-nm process uses
transistors with gate lengths of only 35-nm whereas 50-nm gate
lengths are used in today's Pentium-4 processors. The process
supports memory cells with a density of 10-million transistors
per square millimeter. Intel's 300-mm development fab is
located in Hillsboro, Oregon, and has a 176,000 sq. ft.
cleanroom, which is roughly the size of 3.5 football fields.
For additional information, access: Intel Research
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FILENUMBER: 1144
BEGIN_KEYWORDS
Advanced IC Processes Intel
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DATE: November 2003
TITLE: Advanced IC Processes Being Developed By Intel
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