MICROELECTRONIC SYSTEMS NEWS

FILENUMBER: 1146 BEGIN_KEYWORDS Chemical Mechanical Polishing CMP END_KEYWORDS DATE: November 2003 TITLE: Chemical Mechanical Polishing
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TITLE: Chemical Mechanical Polishing

Designers should be aware of the layout requirements  imposed  by
Chemical Mechanical Polishing or CMP. The move to deep sub-micron
processes   has   placed   conflicting   requirements   on    the
photolithographic  systems employed by wafer vendors. The feature
size of the process is directly proportional  to   the  numerical
aperture  of  the  lenses  used for printing  while the depth-of-
field of the  lenses  is  inversely  proportional.   Hence,  this
situation  has  forced  wafer  manufacturers  to implement severe
planarity requirements on their deep sub-micron  processes  which
can  only  be achieved by using CMP.

CMP removes material from  uneven topography  on  a wafer surface
until a flat (planarized) surface is created, allowing subsequent
photolithography  to  take  place  with   greater   accuracy  and
enabling   film  layers  to  be  built  up  with  minimal  height
variations. CMP combines the chemical removal effect of an acidic
or  basic fluid solution with the "mechanical" effect provided by
polishing with an abrasive material.  The   CMP  system   usually
has  a polishing "head" that presses the rotating wafer against a
flexible pad. A wet chemical slurry containing  a  micro-abrasive
is  placed  between  the  wafer  and  pad.   It is the designer's
responsibility to achieve a minimum density on various layers  to
provide  the  necessary  structural support for this process.  If
the design does not  intrinsically  contain  sufficient  density,
then  additional  "fill"  material  should be used.  However, the
designer must be careful not to use this material in such  a  way
that the primary circuit is affected.

CMP is performed primarily in the interconnect structure  of  the
chip, where it is used multiple times. CMP is especially critical
for the fabrication of copper wiring  structures.  This  advanced
planarization capability enables chipmakers to continue shrinking
circuits  and extends the performance of lithographic tools.

For additional information, access: CMP

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