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TITLE: DVcon CEO Panel Report
EE Times
or
dvcon-panel
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I believe there are about 160 90 nm design being done to date. (Intel, ATI,
Motorola, Fujitsu, ST, NEC, Philips, Infineon...) About 1/2 of those have
taped out (~80).
Of those 80 tapeouts, between 30-40 have taped out using the complete
Cadence SoC Encoutner flow (minus synthesis -- DC is used).
Less than 10 have been taped out using the Magma Flow -- all of those had
FE in the front and DC for synthesis and some (NEC designs) had NanoRoute
in the backend.
That leaves Synopsys with between 30-40 tapeouts as well. Of these, my gut
would tell me most had First Encounter for prototyping and some had CeltIC
for sign-off.
So, is it in the ballpark or safe to say that at 90 nm, Synopsys and Cadence
lead the industry from technology usage standpoint? That Magma is still a
distant 3rd? That regardless of the main EDA vendor used to design at
90 nm, I count of the following being in majority of the flows:
Design Compiler from Synopsys
First Encounter from Cadence
CeltIC from Cadence
Cadence NanoRoute or Synopsys Astro/Apollo
For the Magma designs, most use NanoRoute for final routing
Calibre from Mentor
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Cooley: Given the situation today, would you advise your children to go into
engineering?
Wally: Engineering is a good and productive career.
Brett: Absolutely.
Bernie: It's the single most exciting profession I know of. I see lawyers
and doctors getting bored with their careers. [Laughter] But working in
engineering allows you to meet the brightest people both here in the U.S.
and everywhere in the world. I would most certainly recommend this career
to my kids.
Gabe: If you want to deal with interesting problems, engineering is it. If
you want to be respected, and, on average, you want to make a fair amount
of money, go into something else! [Laughter and applause, long and loud]
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For additional information, access: DeepChip
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FILENUMBER: 1157
BEGIN_KEYWORDS
DVcon CEO panel report
END_KEYWORDS
DATE: March 2004
TITLE: DVcon CEO Panel Report
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