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TITLE: Physical Synthesis of a 10M-gate ASIC Overnight
Sierra Design Automation offers electronic design automation
software for million-gate designs targeted for processes at 90-
nanometers and below. The software, called Pinnacle, uses
physical synthesis to handle 10-million gates flat or up to 50-
million gates for hierarchical designs. Since chip capacity has
quadrupuled from 180-nm to 90-nm, new techniques are needed to
speed physical synthesis. Previously developed approaches rely
extensively on computationally expensive techniques, such as
iterative improvement and brute-force trial-based optimization
resulting in unacceptably long turnaround time of days. Sierra
uses a patent-pending approach which helped Toshiba optimize
placement and routing of a flat 6-million gate design in less
than 12 hours on a 32-bit Linux machine.
For additional information, access: Sierra Design
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FILENUMBER: 1166
BEGIN_KEYWORDS
Physical Synthesis 10M-gate ASIC Overnight
END_KEYWORDS
DATE: May 2004
TITLE: Physical Synthesis of a 10M-gate ASIC Overnight
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