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TITLE: Revised VHDL Synthesis Standard Approved
The 1076.6 standard for VHDL synthesis has been revised and
approved by the IEEE on May 12. The 2004 revision includes
almost every feature of VHDL that can be used to model at the
register transfer level (RTL) and be synthesized. It also
includes enhanced semantic guidelines for modeling flip-flops and
latches. A third component is a set of synthesis pragmas that
provides additional information in the RTL model that a synthesis
tool can use.
For additional information, access:
Synthesis Interoperability Working Group
and
IEEE Standards
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