MICROELECTRONIC SYSTEMS NEWS

FILENUMBER: 1174 BEGIN_KEYWORDS SCHEMATIC-DRIVEN INTEGRATED CIRCUIT DESIGN TOOLS MICROMAGIC END_KEYWORDS DATE: June 2004 TITLE: Schematic-driven Integrated Circuit Design Tools
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TITLE: Schematic-driven Integrated Circuit Design Tools

The popular MicroMagic toolset has now been placed in the  public
domain such that anyone (universities and companies) can download
them at no charge under a BSD license.

SUE (Schematic User Environment) is a graphical environment  that
allows users to enter, visualize, and control large, complex chip
designs. SUE is the first tool to  combine  HDL-based  functional
designs  with  structural design. SUE understands everything from
Verilog  down  to  the  operation  and  physical   placement   of
transistors  and wires.

MAX is an   extremely fast,  industrial   strength,   full-custom
layout  editor    with  the  added  benefit  of a        complete
Tcl/Tk  interface  and  API.  MAX  comes  with  continuous   DRC,
connectivity   tracing,   schematic cross- probing,  wiring tool,
extraction, schematic-driven  layout,  and more.  MAX  reads  and
writes GDSII.

DataPath Compiler (DPC) allows the user to  generate  data  paths
from   a  schematic  view,  and  back  annotate  accurate  timing
information onto the schematic in seconds. DPC can place  custom-
style  "bit  slice"  data  paths minimizing wire lengths for high
performance, and can even include control logic, all using   your
existing standard cell library.

MAX-LS seamlessly integrates the schematic capture  of  SUE  with
the  MAX  layout  editor  schematic-driven  physical  layout.  It
includes interactive cell generation based on LVS and DRC correct
layout,  and  can handle the largest SoC IC design databases. Its
GDSII output can go directly to mask composition products for  IC
fabrication.

The Mega Cell Compiler (MCC) allows users to easily  build  their
own  generators for SRAM's, DRAM's, ROM's, pad rings or any other
regular or semi-regular  structure,  in  just  minutes.  Verilog,
HSPICE,  critical  path  netlists,  and  timing models can all be
generated automatically.

The tools described above  run under either the  LINUX or SOLARIS
operating systems.

For additional information, access: MicroMagic

MicroMagic techfiles  for  the  TSMC-0.25  (1P5M)  and  TSMC-0.18
(1P6M)  processes have been silicon-verified and are available on
the MOSIS secure website.  Both of these were  developed  by  Dr.
Kyusun Choi of Penn. State Univ. who anticipates posting a silicon-
verified techfile for AMI-0.35 this fall.

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dbouldin@utk.edu