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TITLE: Structured ASIC Platforms
Structured ASIC platforms are pre-fabricated ICs except for a few
customizable layers.
The official definition according to the Structured ASIC Association is:
"An integrated circuit architecture and methodology that delivers
reduced entry cost and faster time to silicon using a predefined
arrangement of late-stage mask-customizable logic and pre-
diffused macros and IP."
The rapidly increasing costs for masks and the challenges of very
deep submicron manufacturing make the initial venture into cell-
based ASICs more expensive and riskier than in the past.
Whenever performance higher than that provided by field-
programmable products is needed, structured ASICs may be the
solution of choice. This middle ground, that used to served by
gate arrays, is now re-emerging as platforms with lower cost,
shorter turnaround times, and design flexibility or
programmability.
The design flow begins with the designer using logic synthesis
and simulation to produce a register transfer level net-list
based on the available blocks in a pre-defined platform. The
platform vendor then performs the physical placement (actually
assignment) and routing tasks, pulls pre-fabricated wafers from
inventory and customizes the upper metal layers using masks or
ebeam patterning. This approach isolates designers from many of
the physical design issues such as 3D parasitic extraction,
signal integrity, crosstalk, antenna rules, electro-migration and
IR drops.
Vendors offering a variety of these platforms include:
Altera
AMI Semiconductor
ChipX
eASIC
Faraday Technology
Fujitsu Microelectronics America
Leopard Logic
Lightspeed
LSI Logic [phasing out as of March 2006]
NEC Electronics America
ViASIC
Tool vendors supporting this flow include:
AccelChip
Magma
Synopsys
Synplicity
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