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TITLE: SRC and SIA System-on-Chip Design Challenge
The Semiconductor Research Corporation (SRC) and the
Semiconductor Industry Association (SIA) announced on 11 Nov.
2004 their co-sponsorship of a contest open to North American
university students and faculty to create novel, low-power
system-on-chip (SoC) designs that demonstrate the value of
greater systems integration in integrated circuit design.
Initial 4-page white papers are due no later than 20 January 2005.
Total prizes amounting to $75,000 will be awarded to winning
submissions. Finalists will have an opportunity to have their
designs fabricated by MOSIS in an advanced 180-nanometer CMOS
technology. Major partner companies providing funding for the
fabrication phase of the challenge include: AMD, AMI, Analog
Devices, Cadence, Freescale, IBM, Intel, National Semiconductor
and Texas Instruments.
The contest will be conducted in two phases, with prizes awarded
to the top three contestants in each phase. In Phase One,
contestants will submit chip designs using novel architectures or
subsystems that exploit the advantages of greater systems
integration. Cash prizes of $7,000, $5,000, and $3,000 will be
awarded for first, second, and third place winners.
In Phase Two, the top five entries from Phase One will complete
their layouts and submit their designs for fabrication on a 180-
nanometer, mixed-signal CMOS process at MOSIS. The top winners
will be awarded cash prizes of $25,000, $15,000, and $10,000 for
first, second, and third places.
All monetary prizes will go to the winning teams' Electrical
Engineering departments to help further studies in this important
area. For full information on the contest, access: SoC Contest
For additional information, please contact Becky Spear:
Rebecca.Spear@src.org
Tel: 919-941-9400
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FILENUMBER: 1189
BEGIN_KEYWORDS
System-on-Chip Design Challenge
END_KEYWORDS
DATE: November 2004
TITLE: SRC and SIA System-on-Chip Design Challenge
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