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TITLE: Free Floating-Point Cores for FPGAs
Researchers at the University of Southern California have
developed a library of double-precision floating-point cores for
FPGAs. This library is the first publicly available library to
support all types of numbers representable, all types of
exceptions that can be generated, all rounding modes, and the NaN
diagnostics that are described in the IEEE standard 754, and to
do so in double-precision (64-bit). No special formats are used
internally so there is no need to convert to and from IEEE
format. Cores are available for addition/subtraction,
multiplication, division, and square root. These cores are
parameterized by degree of pipelining and by the features of the
IEEE standard 754 that are implemented. Also provided are VHDL
test-benches. The floating-point cores are coded in VHDL. The
adder and multiplier cores make use of Xilinx Coregen components
(multi-stage adders and multipliers). The divider and square root
cores are described entirely in VHDL.
For additional information, access: Floating-Point Cores
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FILENUMBER: 1198
BEGIN_KEYWORDS
Free Floating-Point Cores FPGAs
END_KEYWORDS
DATE: April 2005
TITLE: Free Floating-Point Cores for FPGAs
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