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TITLE: Reflections on DAC by Gabe Moretti
Published on Gabe on EDA
The 42nd Design Automation Conference just concluded in Anaheim
demonstrated that the EDA industry is in a transition period. As
semiconductor fabrication technology passed the 100 nm mark on
its way to 65 and 45 nm features size, the profile of the market
has changed drastically. Most EDA firms are still experimenting
with different approaches to the new market conditions and in
some cases have succeeded in confusing the DAC executive
committee. In spite of all this over 6,000 attendees got what
they came for: networking with peers, attending panels and papers
presentations, watching demos in the vendors' booths, and
collecting giveaways that, for the most part, were significantly
less extravagant than in previous DAC events. The great majority
of the 240 vendors were satisfied with the quality and quantity
of leads collected on the show floor.
Some Facts About DAC:
Those attending the Sunday evening Dataquest event, a must see
for serious DAC groupies, immediately noticed that things were
different when the traditional Gartner Dataquest ESL Landscape,
one of three segments the firm divides the EDA market, showed
significant growth and diversification over the 2004 version.
Although both Gary Smith, Managing VP, and Daya Nadamuni,
recently promoted to Research Vice President, forecasted growth
for the industry, other analysts and members of the press were
less enthusiastic about the short term financial prospects. In
fact Wally Rhines in presenting the EDAC state of the industry
report, resorted to well delivered humor to enliven what would
otherwise have been a guarded financial picture.
Free Monday was well attended although the Microwave Theory and
Technology Conference, held up the road in Long Beach at the same
time, definitely lowered the number of students and military
personnel taking advantage of the free DAC exhibits. The timing
and close location of the two conferences also impacted DAC’s
Wireless Day, held on Wednesday. Surprisingly only few DAC
exhibitors, notably AWR (Applied Wave Research), Agilent Eesoft,
and Ansoft had to split their teams and exhibit at both
conferences.
The DAC committee reported a greater number of members of the
press registered this year than last year. I have no doubt that
their numbers are correct but there were less European
journalists than in the past, and a few American familiar faces
were missing this year. It was a clear sign that the technical
press is also in turmoil, trying to adapt to new market demands
and the electronic publishing phenomenon. Of course Richard
Goering was there and received special recognition for attending
DAC for twenty years in a row. As Peggy Aycinena pointed out in
her on-line column [1] (www.aycinena.com [2]) I have attended
more DACs than Richard, mostly as a vendor, and not
consecutively, so it is not the number, it is the dedication to
do it every year as a respected journalist that counts. Demos on
Demand teamed with John Cooley (www.deepchip.com [3]) to hold
vendors interviews on the exhibit floor. The companies being
interviewed had to pay a fee in advance for the privilege of
appearing on the video recording and the feed back at the
conclusion of the conference to the Exhibitors Liaison Committee
was that most vendors did not wish to repeat the experience next
year.
Bernard Meyerson, IBM Fellow, Vice President and Chief
technologist of the Systems and technology Group at IBM,
delivered the Plenary session keynote address (see the coverage
by Tets Maniwa on this web site [4]). He had the courage to say
out loud what most people suspected but were afraid to admit:
scaling is dead and system designers need to take a more holistic
approach to design than just cram more transistors on a piece of
silicon and make them operate at higher clock frequencies. This
too was a sign of changing times.
The Big Picture:
The fundamental problem facing the EDA industry is the changing
nature of the markets it serves. Born as an alternative to in-
house CAD and CAE tools, the industry has looked at its customers
as a collection of three distinct groups: IC designers, FPGA
users, and PCB designers. The type of tools they purchased and
the price they were willing to pay for the licenses identified
each group. Vendors did not need to differentiate their marketing
and sales strategy within each group. IC designers, this group of
course includes ASIC designers, purchased design entry,
simulation, verification, synthesis, and place and route tools.
The complexity and size of their designs justified a higher price
point. FPGA designers dealt with smaller designs that were easier
to verify and correct. For a long time they did not need
synthesis and when they did it was a simpler task that required
less directives and a smaller cell library. They did buy design
entry tools, less powerful simulators, and had no need for place
and route, since device vendors performed that task. PCB
designers needed schematic entry and a very good router. Very few
did any simulation with the exception of checking for signal
iintegrity, and engineers placed almost all of the devices by
hand.
EDA companies had to care about their customers the way any good
business cares about its customers: be reasonably responsive to
their needs and keep them happy by providing a reasonable support
organization.
Today things are much different. The line dividing IC and FPGA
designers is blurring as both the size and speed of FPGAs
increase, and the non-recurring costs of ASIC design makes the
choice of FPGA for volumes up to 100,000 pieces an economic
alternative to ASIC design. The integration of PCB and ICs is
also becoming more difficult as the layout on the board, the type
of connections with the package, and the package itself, all have
an impact on the performance of the IC. Additionally, the
complexities of VDSM (very deep sub-micron) design require a
close cooperation among parties that used to see each other
simply as suppliers and customers, not as partners. System
companies, foundries, mask shops, EDA vendors, and equipment
manufacturers must now work together to insure the technical and
financial success of a product. The market is dividing itself in
different segments: design entry, simulation, and verification
produce the RTL netlist that becomes the basis for IC
fabrication, whether designers are implementing an IC or an FPGA.
The tools used to produce the RTL netlist constitute the yet
ill-defined and unfortunately named ESL market. They demand a
different price point and a different support organization than
the rest of the tools. Similarly, PCB designers are maintaining
their own personality and requirements, although some analysis
tools traditionally used in PCB design are now requiring
functionality that only IC designers needed in the past, due to
higher operating speeds and greater product density.
Although this new market profile only impacts four or five EDA
vendors, they represent over 80% of the industry's total annual
revenues, so we cannot ignore the problem. Cadence, Magma,
Mentor, Synopsys, and to some extent Synplicity need to develop a
new approach to the market or suffer the consequences. Unless
they quickly adapt to a new marketing and sales method they will
miss significant revenue opportunities and force a change in the
electronics industry that will be very difficult to reverse and
might be the end of the EDA industry.
Changes I Would Make:
Let's start with DAC. The Executive Committee of DAC needs to
find a way to import more content from two other conferences:
Embedded Systems Conference and SEMICON. Unless more software
engineers and more semiconductor technologists attend and exhibit
at DAC, the conference will offer a partial and distorted view of
the electronics industry. It would also help if the program
committee and the exhibitor made a better effort to attract more
PCB designers to DAC. Relegating them to their own shows is
ignoring the holistic approach to system design Dr. Meyerson so
eloquently proposed.
I do not like the ESL name given to design efforts above RTL of
abstraction. The unfortunate label overtly ignores the software
component of the system. I have yet to find a software engineer
that describes his or her work as doing electronic design. They
all correctly think they are producing software, whether it is
embedded or application specific and residing in some external
storage system. In addition any good architect would also
consider the thermo-mechanical implications when deciding how to
partition and package a system, so the name the EDA industry now
uses for architectural design is clearly non-descriptive and too
electronic hardware centric.
I would also suggest that Dataquest discard the labels it uses
for its market segments and use very basic descriptions. ESL
should be called ADV for architecture, design, and verification,
and CAE should be called DFM for development for manufacturing.
The third segment, now called CAD/CAM is a catchall collection of
analysis tools that should be part of DFM or belong to the third
segment: PCB design and development. The advantage of this new
method is that it aligns much better with the pricing methodology
I propose. Using the new nomenclature makes it clear that EDA
vendors, who traditionally have focused on hardware design to
address the ADV market, need to collaborate with companies in the
software development business and even in the mechanical drawing
market in order to provide a development environment that truly
supports the development of a product architecture. The goal is
to develop an environment that offers a computer based accounting
trail of the refinement steps leading to a manufacturable
representation of the product.
The most important priority on the part of both EDA vendors and
semiconductor companies is to establish a standard RTL handoff
method, to clearly separate ADV tools from the work required to
prepare a design for manufacturing.
Much has been said and written about a new licensing method that
would allow EDA vendors to capture some of the profits generated
by their customers on a risk-share basis. The problem is that
establishing a clear relationship between ADV tools and
manufacturability and yield is difficult at best. We have no data
that shows how a particular design method can produce better
yielding wafers than another. I am sure that given enough time
and experience with VDSM designs we can discover preferred design
methods, but EDA cannot wait that long. Annual revenues that are
just over 1% of the semiconductor industry revenue level cannot
sustain the amount of research and development required to
support VDSM designs in a cost effective manner.
DFM tools can, instead, be directly related to silicon success.
In fact, at the VDSM level EDA tools and methods must be
integrated with the foundry knowledge of the process
characteristics, statistical variations, and reticles production.
Therefore EDA tools prices can be factored directly into the
production costs of a foundry and can then be charged to the
customer. Both the foundry and the EDA vendor can then share the
revenue in a manner that is established using known accounting
methods. Of course this means that every foundry customer has to
choose a set of tools from one EDA company that either owns all
of the required tools or acts as a consolidator and provides the
foundry with a unique source of tools and methods. In fact this
is the most cost effective way to progress an RTL netlist to
silicon in the VDSM world, since the complexity of project
management grow exponentially with the number of parties involved
in the development.
The Big Five at DAC:
I decided to spend time with the five largest publicly traded EDA
companies and observe their approach to DAC in light of the new
business climate prevailing in our industry. Since they are
responsible for over 80% of the industry annual revenue, the
fortunes of the industry are directly related to their business
and technology priorities.
Cadence:
Cadence drastically modified its DAC presence from previous
years, and, whether on purpose or by accident, differentiated its
product line between pre- and post-RTL tools. The acquisition of
Verisity provided, I am sure, a natural vehicle for this action,
since the Verisity booth was morphed into the Cadence Incisive
booth. Most of the marketing work for its tools falling under my
DFM label was done in suites at the Hilton hotel, although
attendees could find some overview of the tools on the exhibit
floor. I attended the Monday morning breakfast that Cadence held
for financial analysts and press. The presentation was a sequence
of four marketing speeches, although only one speaker officially
held a title that had anything to do with marketing. During this
event, Cadence announced its Torino initiative. This was most
pleasing to me, since it is not often that my native town
receives the acknowledgment it deserves, but I left wondering how
the choice of the name was received by Alberto Sangiovanni
Vincentelli, one of the few technical leaders at Cadence, who was
born in Milano, Torino archrival in soccer and other things
important to Italians. I have not had the opportunity to discuss
this un-enlightened internal event with Alberto, but I look
forward to do so at the appropriate time. The most positive
experience I had in my interaction with Cadence was my meeting
with Jim Miller Senior Vice President Development. Jim came from
outside the industry a few months ago and has already learned a
remarkable amount about our industry. Additionally he possesses
the rare skill of actually understand marketing issues while in
charge of an engineering group. We discussed the strategy Cadence
will follow to increase revenues in the DFM market. Here I must
digress slightly and take the opportunity to differ from Peggy
Aycinena. She just wrote an article on her web site [5] that
justifies the acquisition of Cadence by TSMC. I think that
instead of being good for both companies, such an event would
hurt TSMC business and would put Cadence employees out on the
streets. Although both companies need to learn how to play
effectively with one another and establish the kind of business
relationship I described above, neither can afford to be so
parochial to merge and thus limit their available customer base
to the significantly smaller set that represents their common
customers. Cadence needs to play nice with TSMC, but also with
other foundries and IDMs like Intel, TI, and STMicro, or it will
become a much smaller company. Jim Miller and Ted Vucurevich,
Cadence’s CTO, understand this. I have not spoken with Mike
Fister, I think he lives in another time warp and materializes in
our dimension only at very carefully choreographed occasions, so
I cannot tell what he thinks, but at least two of his senior
executives understand most of the implications. It is clear that
DAC in its present form and with its present attendees profile is
not conductive to pursuing this type of business on the exhibit
floor, so although the absence of a large monument to Cadence
Corporate magnificence is regrettable, I finally understood it.
Cadence seemed taken by surprise by Synopsys decision to join the
Si2 Open Access Coalition. They should have prepared better
forthis eventuality, regardless of the degree of probability that
it would come to pass. The combination of Synopsys willingness to
interface its tools to the Open Access data base combined with
the advances made by Silicon Navigator in developing a framework
of tools around Open Access are bringing into question Cadence's
strategy to open its design data base to the public.
I am not enthusiastic about Cadence's Incisive strategy. No one
could explain to me the Verisity purchase in engineering terms,
although Jim Miller did make a lot of sense presenting it in
terms of market segment acquisition. My problem with Cadence is
that it has been a market follower for over five years, and has
not shown the engineering leadership it once possessed in ADV
tools. In the last four years it has been third in adopting first
SystemC and then System Verilog, after Synopsys and Mentor. We
will see what Torino brings. I hope they did not choose the name
just to increase my interest in their doings!
Magma Magma suffers from being the “underdog” and from the EDA
environment that encourages brilliant engineers to leave a large
company to join a startup and make their fortune. Unfortunately,
whether willingly or not, some engineers bring with them the
knowledge they applied at their previous employer. I am not
making a legal point here, nor am I choosing sides in the
existing legal dispute, I am just observing that some of these
problems are self inflicted, and that the process of patent
granting and enforcement can stand much improvement. Magma is
addressing the market almost exclusively by promoting the
strength of its technology. It is isolated: does not play well
with any of the other big four. I do not know if this is by
design, chance, or the result of actions on the part of the
others, but it is a fact. Magma has toned down its glitz at DAC.
Their booth was elegant and understated, the press dinner (it was
my first time I attended it) was good and the presentation brief.
It is working hard on new technologies and gives no indication
whatsoever of planning to roll over and play dead. Their major
obstacle will be to quickly establish the kind of foundry
relationships that both Cadence and Synopsys enjoy. If they fail
their death will be much slower than that of Monterey Design
Systems, but just as certain especially since they have no
presence in the ADV market segment.
Mentor:
The company sees no reason to change its course. It offers a
collection of point solutions. Three of its businesses,
Simulation, PCB design and RET generate the greater portion of
its revenues, and new tools announcements are aimed at market
segments of ever decreasing size. At its press and analysts
dinner it focused on Catapult C a product that generates a RTL
netlist from an ANSI C design description. Not a very unique
idea, considering Celoxica, Forte, and Coware also play in that
space. I know that the dialects of C are all different, some more
extensive than others, but in the final analysis the C
description must represent a synthesizable circuit. The same
presentation also introduced Questa, a platform that seems to
have copiedthe Cadence Incisive idea. Mentor does dominate the
simulation market for FPGA design and the same product can handle
the most complex ASIC design in a multilingual environment, yet,
for some reason, it has not successfully clinched the synthesis
market for FPGA. Go ahead Wally, make peace with Ken and buy
Synplicity or at least integrate your tools with theirs. You will
both be happier afterward. This will also help you to forever
bury the John Cooley donut curse. Calibre continues to lead its
market, but unfortunately when you are number one there is only
one way to go. Mentor needs to continue to invest significant
engineering talent to complete Calibre with other products that
help analyze and verify silicon against design, process, and mask
features.
Synopsys:
Due to its long established leadership in synthesis, Synopsys
enjoys very good relationships with most foundries and IDMs, so
on paper it has an advantage in establishing the closely
integrated development environment needed by system companies
utilizing VDSM processes. On Wednesday June 15th Synopsys
surprised Cadence by joining the Si2 Open Access Coalition thus
laying the groundwork to lower the barrier to access Cadence's
installed base. Judging by the lack of comments on the part of
Cadence, I think the lement of surprise worked in Synopsys favor.
Synopsys is continuing to execute on its strategy to build a
strong inventory of IP blocks, covering both functional and
verification IP. My discussions with Aart De Geus confirmed his
belief that IP will be a significant differentiator in the next
few years and that a new type of IP might in fact play a
strategic role in convincing foundries to implement the Synopsys
flow. This year Aart and his fellow musicians were a feature
group at the Denali Party. Of course Denali Software is the
market leader in verification IP for memories. Remembering the
failed attempt by Synopsys to acquire Mosys, I wonder if next
year Aart and his band will be the feature group at the
Synopsys/Denali Party!
Synopsys is also recovering from its mishandled attempt to
introduce SystemC to the EDA industry. It realized that SystemC
was only a partial technical solution and that it would never
reach the sales volume required by the company to maintain its
presence in a market, and made a timely switch to System Verilog.
With the cooperation of Mentor, Synopsys is succeeding in
establishing this new language as the preferred tool for hardware
design at an abstraction level higher than register transfer.
Synplicity:
According to Andy Haines, VP of Marketing, the company continues
to enjoy a leadership position in FPGA synthesis, in spite of the
annoying attempts by both Altera and Xilinx to extend the power
of their EDA tools. The fact that the price of an FPGA device is
higher than it should because both these companies find it
necessary to make design tools available for practically free to
their customers has not yet bothered any large system company. It
should, since this behavior is a clear example of the incapacity
of the EDA industry to raise its revenues. As long as EDA tools
are seen as marketing tools used to promote silicon sales, they
will be heavily discounted and hurt everyone in the long run. The
increasing non-recurring costs of ASIC design in VDSM are
fostering a growth in the use of FPGA devices. The shorter market
time of consumer products is also working in favor of FPGA use,
so Synplicity is well positioned for growth.
Synplicity is also taking advantage of the growing market for
structured ASIC and offers support to PCB designers in
integrating FPGA devices on the board. It lacks front-end tools
and could not easily displace Mentor’s Modelsim simulator in the
FPGA market. The same comment I made about Mentor is valid here.
Ken, bury the hatchet and talk to Wally. There are ways to
cooperate that do not involve a takeover if you really value your
independence. A tool flow that integrates Mentor and Synplicity
tools would be a formidable competitor in both the FPGA and the
structured ASIC markets.
Links:
[1] http://www.aycinena.com/index2/ideas.html
[2] http://www.aycinena.com
[3] http://www.deepchip.com
[4] http://www.gabeoneda.com/node/21
[5] http://www.aycinena.com/index2/index3/why%20tsmc%20should%20buy%20cadence.html
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FILENUMBER: 1226
BEGIN_KEYWORDS
DAC Gabe Moretti
END_KEYWORDS
DATE: July 2005
TITLE: Reflections on DAC by Gabe Moretti
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