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TITLE: FPGA Power
Dynamic power consumption occurs on each clock edge when the FPGA
is actively computing while static power consumption occurs due
to leakage while the internal flip-flops are just holding data.
Over the past few years, dynamic power consumption per gate of
FPGAs has continued to drop, but it has been largely offset by
increased density. Meanwhile, leakage current has increased with
the decrease in transistor feature size and is now a significant
percentage of the total power consumption of FPGAs. The latest
low-cost FPGAs such as Xilinx's Spartan-3, Altera's Cyclone-II,
Lattice's EC/ECP/XP, Actel's ProASIC-3, and QuickLogic's Eclipse
II families are all aimed at high-volume applications which often
run on batteries or have limited cooling capability or restricted
power supplies, which makes lower power operation an absolute
necessity. Inside an FPGA very thin oxide layers leak current
even when transistors are not switching. To avoid the
possibility of thermal runaway in 90-nanometer processes, Xilinx
uses a thicker oxide in its Virtex-4 family for transistors
involved in the routing and configuration circuitry which do not
require rapid toggle rates, as they generally remain in a
constant state once configured. Altera dropped the traditional
4-input LUT in favor of a 7-input variable adaptive logic module
when developing its 90-nanometer devices. Thus, the new devices
have decreased logic granularity and reduced routing-related
power overhead. The devices also employ low-K dielectrics and
longer transistors with increased Vt for non-performance-critical
paths.
On the tool side, every FPGA vendor offers software that will
help estimate power consumption based on a spreadsheet. The
designer supplies estimates of parameters like logic, memory, and
I/O utilization, clock frequencies, toggle rates, and operating
temperatures. The tool then produces an estimate of power
consumption for those conditions. While these early estimates are
the least accurate, they can serve as the basis for deciding
which FPGA family to utilize. Xilinx provides Web Power Tools
for pre-implementation power estimates and XPower tools for
post-implementation power analysis. These tools deliver results
that correlate well to actual silicon measurements when used
correctly. The best power estimates are those done on a completed
and routed design that has been loaded into the XPower tool and
stimulated with a functionally accurate set of stimulus vectors.
However, Xilinx Web Power Tools help estimate total power
consumption accurately prior to design implementation. System
architects can estimate power using high-level design details and
make intelligent design choices on clock frequencies,
implementing a function using hard IP or logic, type of I/O
standard to use, and other factors. The Web Power Tool relies
exclusively on the user's estimates of their FPGA design
parameters such as utilization, toggle rates, operating
conditions, etc. For additional information, access:
Xilinx Power
While power optimization tools have been available for ASIC
design for a while, automated power reduction is still a
relatively immature science for FPGAs. In ASICs, clock and power
gating, buffer sizing, and voltage scaling can be employed by
automated power optimization tools. In FPGAs, however, the
options are somewhat limited by the underlying architecture and
the opportunity for improvement is reduced by the dominating
presence of static power related to configuration circuitry.
Nevertheless, since power is becoming a hot topic in FPGA design,
there is serious research underway into techniques and tools. An
excellent article on this topic appeared in the November 2005
issue of the IEEE Transactions on Computer-Aided Design (vol. 24,
issue 11, pp. 1712-1724).
For additional information, access: FPGA Journal
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FILENUMBER: 1239
BEGIN_KEYWORDS
FPGA Power
END_KEYWORDS
DATE: December 2005
TITLE: FPGA Power
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