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TITLE: Text on Verilog Synthesis and Verification
"Verilog Digital System Design: RT Level Synthesis,Testbench and
Verification" is a new text (ISBN: 0-071-44564-1) written by
Prof. Z. Navabi of Northeastern University and published by
McGraw-Hill.
The book comes with
the complete simulation and synthesis tools from Altera (Quartus
II and ModelSim). In addition to being a book for professional
engineers, this book is being targeted for university adoption
and educational use. Presentation slides and solutions to the
end of chapter problems are available for instructors. For
adoptions and desk copies, please contact the author at:
navabi@ece.neu.edu
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FILENUMBER: 1243
BEGIN_KEYWORDS
Text Verilog Synthesis Verification
END_KEYWORDS
DATE: February 2006
TITLE: Text on Verilog Synthesis and Verification
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