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TITLE: Crosstalk Analysis Tools for ASICs
ASIC designers are reconizing that signal integrity issues are
increasingly significant when designing in 90-nm and below CMOS
processes. Crosstalk-induced delays as well as power noise due
to voltage drop are all of concern and are being addressed by new
electronic design automation tools. Designers are being
encouraged to allow more time for signal integrity closure,
develop a better understanding of the issues and adopt avoidance
techniques as well as after the fact analysis. Synopsys offers
PrimeTime-SI and Cadence offers CeltIC for crosstalk and noise
analyses. Designers are finding that in a 90-nm process, eighty
percent of the capacitance can be due to coupling between
adjacent wires either on the same layer or between layers. One
tactic is to practice techniques which prevent or avoid these
problems by careful placement and routing of wires. The
strongest coupling occurs when the agressor wire is switching and
the adjacent victim wire has a weak signal. The coupling is
reduced either by increasing the separation of these wires or by
using a stronger driver on the victim wire so the agressor
interferes less with its activity. Clocks are often becoming
aggressors on nets. For additional information, access:
Synopsys and Cadence
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FILENUMBER: 1248
BEGIN_KEYWORDS
Crosstalk Analysis Tools for ASICs
END_KEYWORDS
DATE: February 2006
TITLE: Crosstalk Analysis Tools for ASICs
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