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TITLE: Quixilica Floating-point Cores for Xilinx FPGAs
Cores are supplied as compiled netlists with a VHDL wrapper.
Where cores are parameterised, multiple netlists are provided and
the VHDL wrapper uses generics to select the correct netlist.
Cores are supplied with simulatable VHDL models that can not be
synthesized. The cores have been designed to be resource
efficient on Xilinx FPGAs and this requires device specific
optimisations to be made. Hence, they will not work directly on
other FPGAs. DSP cores are supplied with a software bit-true
model for numerical analysis with interfaces for Matlab and
C/C++. Software programmable cores are supplied with
configuration functions for generating the data required to
configure the core as well as examples demonstrating the use of
the core. The FPU uses single-precision arithmetic. All double-
precision code is handled through software emulation.
Cores are made available for an evaluation period by sending
email to sales@quixilica.com.
For additional information, access:
QinetiQ
Quixilica
Floating-Point Cores (13-page pdf)
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