MICROELECTRONIC SYSTEMS NEWS

FILENUMBER: 1261 BEGIN_KEYWORDS Automated Synthesis Multi-Core Processor Systems PARO END_KEYWORDS DATE: May 2006 TITLE: Automated Synthesis of Multi-Core Processor Systems
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TITLE: Automated Synthesis of Multi-Core Processor Systems

Researchers  at  the  Friedrich-Alexander  University  (FAU)   in
Germany  are  conducting  a  research  project  to  automate  the
synthesis of multi-core processor systems.

The PARO (Piecewise Linear Algorithm  and  Architecture  Research
and  Optimization)  project  is  based  on  a class of algorithms
called piecewise  linear  algorithms  that  can  be  mapped  very
efficiently    on    massively   parallel   architecures.   These
architecures are known  as  VLSI  processor  arrays  or  systolic
arrays whose principal properties are:

    * high degree of parallelism
    * regular structure
    * local interconnect

In the area of systolic arrays, a lot of research  was  performed
in  the  eighties  and nineties. Algorithms from many application
areas were implemented  as  systolic  arrays,  e.g.,  RADAR  data
processing  (Kalman  filtering)  or  linear  algebra  (matrix and
vector operations).

Unfortunately, the class of systolic arrays is too rigid to allow
complex   algorithms  to  be  implemented  efficiently.  However,
semiconductor technology will allow the implementation of  10-100
32-bit  processors  on  a  single  die within the next few years.
Mobile  telephony  will  require  several   thousands   Mips/Watt
efficiency  in  order  to  save  battery power and allow internet
technology to  become  ready  for  mobile  devices.  Current  DSP
(digital  signal  processor)  technology  cannot  cope with these
requirements. In the above  and  many  other  areas  of  embedded
computing,  such  systems  must be carefully designed in order to
meet cost, power efficiency and speed  requirements.   Therefore,
FAU  researchers  plan  to  provide  support  for  the  automatic
synthesis of such tightly coupled multiprocessor systems that may
be  implemented on a single chip.  They seek to provide solutions
to the following unsufficiently solved problem areas:

    * affine mapping methodology
    * design space exploration of space-time transformations
    * regular hardware synthesis

Testing of the methodology will be conducted using reconfigurable
logic since ASICs are too inflexible and expensive.

For additional information, access: PARO

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