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TITLE: Verification Methodology Manual for SystemVerilog
The Verification Methodology Manual (VMM) for SystemVerilog by J.
Bergeron and E. Cerny of Synopsys and A. Hunter and A.
Nightingale of ARM is a book from Springer that documents
functional verification techniques. The VMM provides developers
with specifications for a library of verification functions to
speed development and enable interoperable verification
components. It helps enable chip development teams to achieve
measurable functional coverage goals in less time with less
effort, giving verification engineers and managers the confidence
to tape out complex system-on-chip (SoC) and silicon intellectual
property (IP) designs.
For more information, access: Springer or SystemVerilog.
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