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TITLE: Radiation-Hardened Structured ASICs
Military and aerospace IC applications typically have additional
requirements of high-reliability, operation in high consequence
applications, long operational lifetimes, and radiation hardness.
In an effort to address these issues for internal system
applications, Sandia National Laboratories has developed a
radiation-hardened structured ASIC platform, designated as VA260.
The VA260 is implemented in Sandia' 0.35micron, 3.3v, radiation-
hardened, CMOS-SOI technology. The platform offers 260K logic
gates, 354K bits of SRAM, 352K bits of ROM, an on-chip
oscillator, and 170 configurable I/O. The chip architecture is
based on pre-defined, pre-characterized logic tiles. Base wafers
are pre-fabricated through metal-2. User designs are customized
at the via-2 layer. The remaining standard metal layers can be
quickly fabricated. Parts are then tested, packaged, and made
available to the user at a reduced cost and time versus a typical
standard cell design flow.
For additional information, access: Sandia
Honeywell is using its 150nm rad-hard SOI technology together
with Lightspeed Semiconductor's structured array technology to
develop a structured ASIC solution for rad-hard applications.
Honeywell's Standard Cell Library cells embedded in Lightspeed's
proprietary fabric, provides shortened design lead times with
rapid timing closure, as well as rapid ASIC fabrication cycles
with 5 custom masks per design. The initial version of the
Honeywell RADiance Structured ASIC (S-ASIC) array will contain
2.5M bits of SRAM and 1M bits of post-synthesis Logic. The
initial version of the Honeywell S-ASIC will be followed by two
other arrays, with different mixes of SRAM and Logic.
For additional information, access: Honeywell
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FILENUMBER: 1270
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Radiation-Hardened Structured ASICs
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DATE: June 2006
TITLE: Radiation-Hardened Structured ASICs
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