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TITLE: Advanced Verification Methodology for SystemC and SystemVerilog
Mentor Graphics has released Questa 6.2 which is a verification
platform implemented in both SystemC and SystemVerilog. Advanced
Verification Methodology (AVM) is an open, non-proprietary
methodology that supports a true system-level-through-RTL design
and verification flow. AVM features an object-oriented coding
style to reduce the amount of testbench code and a modular
architecture to enable reuse.
AVM uses a layered architecture. The lowest level of abstraction
connects to the design under test (DUT) via its pins and contains
transactors, like drivers, monitors, and responders. The level
above implements the test environment and contains stimulus
generators, constraints, and both master and slave test modules.
The two layers communicate via transactions. The third level of
abstraction is the analysis level. It contains coverage
collectors, scoreboards, performance analyzers, and golden
models. It communicates with the environment level through either
untimed or partially timed transactions. The upper level of
abstraction contains the test controller that manages the
verification through untimed transactions with the analysis
layer.
For additional information, access: Functional Verification
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FILENUMBER: 1273
BEGIN_KEYWORDS
Advanced Verification Methodology SystemC SystemVerilog Questa
END_KEYWORDS
DATE: July 2006
TITLE: Advanced Verification Methodology for SystemC and SystemVerilog
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