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TITLE: Text on Design for Testability
A new text entitled "VLSI Test Principles and Architectures:
Design for Testability" co-edited by Laung-Terng Wang, Cheng-Wen
Wu and Xiaoqing Wen is now available from Elsevier (ISBN: 0-12-
370597-5). This book addresses techniques appropriate for designs
at 90-nm and below and serves as a comprehensive guide to new as
well as existing, well-proven DFT techniques that will show the
readers how to design a testable and quality product, drive down
test cost, improve product quality and yield, as well as speed up
time-to-market and time-to-volume. It covers industry practices
commonly found in commercial DFT tools but not discussed in other
books including at-speed testing for scan and logic built-in
self-test (BIST) applications, test compression for reducing scan
test cost, memory fault simulation, DRAM BIST, memory built-in
self-repair (BISR), and future test technology trends. Numerous,
practical examples in each chapter illustrating basic VLSI test
principles and DFT architectures make this book a very valuable
reference for engineers and managers practicing in the DFT field.
For additional information, access: Elsevier
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FILENUMBER: 1285
BEGIN_KEYWORDS
Text Design for Testability
END_KEYWORDS
DATE: August 2006
TITLE: Text on Design for Testability
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