=================================================================
TITLE: Texts on SystemVerilog for Design and Verification
Two texts on SystemVerilog are now available:
"SystemVerilog for Design"
by S. Sutherland, S. Davidmann and P. Flake
2nd edition, 2006, ISBN: 0-387-33399-1
SV-Design
SV-Training
"System Verilog for Verification"
by T. Fitzpatrick, A. Salz, D. Rich and S. Sutherland
1st edition, 2006, ISBN: 0-387-25571-0
SV-Verification
=================================================================