MICROELECTRONIC SYSTEMS NEWS
FILENUMBER: 206
BEGIN_KEYWORDS
mosis micromachining cmos circuit
END_KEYWORDS
DATE: april 1993
TITLE: Micromachining Using MOSIS
Micromachining Using MOSIS
(Contributed by MOSIS)
MOSIS can now support CMOS-compatible micromachining to realize
microelectro-mechanical systems (MEMS) and devices such as
suspended corners, cantilevers, and pixels (see IEEE Circuits and
Devices Magazine, November 1992 issue). The users' chip designs
are fabricated through MOSIS and the user may perform the post-
processing, maskless, anisotropic etch by one of the following
two ways:
(1) By following the directions in the following references:
a.) M. Parameswaran, H. P. Baltes, Lj. Ristic, A. C. Dhaded,
and A. M. Robinson, "A New Approach for the Fabrication of
Micromachined Structures," Sensors and Actuators, Vol. 19,
pp. 289-307, 1989.
b.) M. Parameswaran, A. M. Robinson, D. L. Blackburn, M. Gaitan,
and J. Geist, "Micromachined Thermal Radiation Emitter from a
Commercial CMOS Process," IEEE Electron Device Letters,
Vol. 12, No. 2, February 1991.
(2) By consulting with:
Michael Gaitan
NIST
Technology Bldg, Rm B-360
Gaithersburg, MD 20899
TEL: (301)975-2070
FAX: (301)948-4081
EMAIL: gaitan@sed.eeel.nist.gov
To support these designs, two new layers called "open" and "etch
stop" are used. These layers allow for exposing the silicon sur-
face to the ambient after fabrication. When the chips are
delivered, the post-processing etch is performed. This etches
the exposed silicon surface anisotropically which realizes the
suspended structures. For successful designs, the placement of
these layers are crucial, as discussed below.
To design with the open and etch stop layers:
When designing micromachine devices, there are four basic design
considerations. They are as follows:
1. The resulting cavity for one, designed, open area (also
called a tile),
2. The resulting cavity for multiple, designed, open tiles,
3. The support beams for pixels, and
4. The lateral etch stop.
With these design considerations in mind, the design layout of
any structure, either simple or complex, can be achieved with
CMOS-compatible micromachining techniques, as discussed next.
A. The resulting cavity for one, designed, open tile
The resulting cavity for one, designed, open tile depends
upon its alignment with respect to the x-y axes. The rule for
determining the resulting cavity is as follows: the resulting
cavity for one, designed, open tile will be an inverted pyramid
whose inverted base is the smallest, aligned rectangle which can
enclose the vertices of the defined geometry.
If the open layer is rectangular and aligned with the x-y
axes, then the resulting cavity will be an inverted pyramid with
the designed, open rectangle as its inverted base.
If the open layer is defined with a geometry other than a
rectangle and with a misalignment with respect to the x-y axes,
then (as the rule implies) the rectangular, inverted pyramidal
base will be aligned with respect to the x-y axes and will be the
smallest rectangle that can enclose the vertices of the defined
geometry.
B. The resulting cavity for multiple, designed, open tiles
The above rule applies to one open area. For two or more
open areas defined in close proximity to each other, the above
rule is expounded upon to also include more than one open area to
determine whether or not the resulting cavity will be merged or
distinct. Therefore, the rule for one or more open areas is: The
resulting cavity will take the shape of an inverted pyramid whose
inverted base is the smallest, aligned rectangle which can en-
close the vertices of the defined geometry(ies), assuming the
resulting cavities for the individual geometries intersect in the
case of multiple geometries. In simpler terms, for more than one
open area, it is first necessary to use the rule for one open
tile to draw the smallest, enclosing rectangle for each open area
defined in the vicinity. If any of these smallest, enclosing
rectangles intersect or touch each other, then during the post-
processing phase, the two cavities will merge. After a suffi-
cient amount of time in the post-processing etch solution, the
final, resulting cavity will be an inverted pyramid with a rec-
tangular, inverted base which is the smallest, aligned rectangle
which encloses all the vertices of the individual, intersecting,
open areas.
C. Support beam design for pixels
Pixels look like a trampoline with the suspended portion
in the center held up by support beams. For a successful support
beam design, the support beam edges need to be designed using po-
lygons or designed using many small, even, staircase-like steps
at an angle (generally 45 deg) with respect to the x-y axes in
order to have intersecting, open-pit regions which will form one
large rectangular pit after the anisotropic etch. We believe
that mechanical failure may result if the support beam edges are
designed with several irregular, stagger steps.
A smooth polygon can define the misaligned, angular edge
of the support beam. It has been found that such a polygon
geometry can be utilized in non-Manhattan-type designs (designs
that can be represented by lines which are not drawn parallel and
perpendicular to the primary wafer flat) for CMOS-compatible mi-
crostructure layout. However, this technique can be employed
only if all the angles made by the polygon are obtuse, that is,
greater than or equal to 90 deg.
Many small staircase-like steps can be used to define the
support beam edges. One micrometer steps can be designed rapidly
using automated commands on any CAD system. The stagger steps
mentioned previously are irregular and easy to design, however,
with a few extra keystrokes a nice staircase can be built that
will not undergo severe stress and eventual failure. For the CAD
tools requiring Manhattan-type layouts in which the design
geometries are represented by lines which are drawn parallel and
perpendicular to the primary wafer flat, the designs using many
small steps is the only choice. Taking this to the extreme, sup-
port beam edges using a submicrometer dimension equivalent to the
step-and-repeat distance of the E-beam writer can be used in
which case the polygon design and the staircase design are
equivalent. However, using submicrometer dimensions with some
CAD design tools can be time consuming.
D. The lateral etch stop
With commercial CMOS-compatible micromachining, micros-
tructures and support circuitry can coexist on the same sub-
strate. Etching can be prevented from proceeding towards the
circuit area by monitoring time and etch rates. But, this re-
quires precise monitoring of the etchant. As a result, the la-
teral etch stop technique described in this section finds exten-
sive use when there is an occurrence of both circuits and micros-
tructures. This technique is very effective and reduces the need
to have precise process control.
It is well known that silicon which has been patterned
with heavily doped boron (p+) can act as an etch stop during an-
isotropic etching. This property is used to generate a lateral
etch stop in CMOS-compatible micromachining. Boron implantation
is a necessary step in the standard CMOS process sequence since
it is normally used to form the source/drain regions of PMOS dev-
ices. Thus, the etch stop consists of the active area mask
(which etches away the oxide on the substrate for a successful,
subsequent implantation) and the slightly oversized p+ implant
mask used in the standard process.
Considering an isolated, open area, it should be noted
that the etch stop is effective only if it is designed parallel
to its neighboring, open edge that is parallel or perpendicular
to the primary wafer flat. If the etch stop is parallel to a
misaligned, open edge, then because of the undercutting nature of
anisotropic etchants, the etch stop will not work. If consider-
ing more than one open area with intersecting cavity regions, the
final, resulting cavity can be determined using the resulting
cavity rule for multiple, designed open tiles. The edges of this
final, resulting cavity will be parallel or perpendicular to the
primary wafer flat. The etch stop can then be designed surround-
ing the perimeter of this final, resulting cavity. In summary,
the rule for the placement of the lateral etch stop is: surround
the perimeter of the final, resulting cavity with the etch stop.
A typical etch stop is 8 to 10 um in width.
To perform the post-processing etch:
When the chips are received from MOSIS, a post-processing aniso-
tropic etch is performed to realize the suspended structures. A
knowledge of the effect of this etchant on the placement of the
designed, open areas is needed in order to design suspended
corners, cantilevers, and pixels.
The etchant used, EDP (ethylene diamine-pyrocatechol-water), was
chosen because both SiO2 and Al can be used as masking materials.
This is important since the surface of CMOS chips are covered by
SiO2 for passivation while the bond pads are aluminum. There-
fore, the only areas exposed to the etch are the open regions
designed in the CAD layout. These factors give rise to a mask-
less etch procedure for realizing the suspended structures in
standard CMOS. [EDP can be purchased premixed from the Transene
Company, Inc., part number PSE-300-F.]
In the case of a rectangular opening in the SiO2 that is aligned
to the x-y grid system of the CAD layout, the opening exposes the
Si surface initially. After some intermediate time in the aniso-
tropic etch, a pit is formed with a flat bottom. The side walls
of the pit are bounded by the {111} planes and form a 54.74 deg
angle with respect to the silicon surface plane. The material
being etched is primarily at the bottom of the pit. After some
final time the 4 walls intersect at a point, halting further
etching.
The reason the side walls of the pit form a 54.74 deg angle with
the surface is that the etch rate of the etchant varies with the
direction in the silicon crystal lattice; hence, the term aniso-
tropic etch. Of primary importance is the fact that the etch
rate is significantly slower in the <111> direction as compared
to the <100> direction. The approximate ratio for the etchant
used in this work for these two directions is 1:35. Therefore
the {111} planes can virtually be used as etch stops. There is
some undercutting of the Si-SiO2 surface because the etch rate is
not completely negligible in the {111} direction. This undercut-
ting can be minimized by using a p+ boron implant at the perime-
ter of the open area.
An etch procedure follows:
Emerse the chips in a gently stirred EDP solution at 92 deg C in a
reflux container for 30 minutes or more depending on the size of the
cavity. (I.e., for a 150 um square open cavity, about 80 minutes is
needed.) This is the step that creates the suspended structures.
The actual time spent in the EDP solution is a function of the device
size. Although the etch step is self limiting, it is standard
practice to minimize the time in the etch solution.
NOTE: When the chips are received from MOSIS, if any native oxide
is in the open areas they can be dipped in a 2% buffered HF solution
for 10 seconds, however, this step has typically not been needed for
chips received from MOSIS.
For further information and technology files:
Please initially direct any questions to MOSIS, by sending an at-
tention message to 'mosis@mosis.edu'.
MOSIS will release an revised 'scmos' Magic technology file to
support the open and etch stop layers. This technology file will
be obtainable through MOSIS using the information request or
anonymous ftp methods.
Tanner Research will also release support for MEMs design with
L-edit.
dbouldin@utk.edu
Return to MSN Home Page