MICROELECTRONIC SYSTEMS NEWS



FILENUMBER: 3010
BEGIN_KEYWORDS
l-edit mosis asic tanner mask standard cell drc lvs
END_KEYWORDS
DATE: july 1993
TITLE: ASIC Tools Available from Tanner Research

ASIC Tools Available from Tanner Research 

(Contributed by Jim Lindauer of Tanner Research)

ASIC Layout Editor and Verification Package, L-Edit Version 5.0:

L-Edit is an interactive, graphical mask layout editor  for  ASIC
design  that  is  fast,  easy  to use, and fully hierarchical.  A
full-featured, high performance tool, L-Edit handles an unlimited
number  of  mask layers, levels, and cells.  L-Edit provides all-
angle, 45 degree, and orthogonal drawing ability.  The  user  en-
vironment  is  fully customizable, including color palette, stip-
ple, fill, and outline patterns.  Editing features include  edit-
in-place  for  the editing of instances within their hierarchical
content.  This allows a cell that is levels below the  top  of  a
design,  to be edited from the top level and maintain the view of
its context.  A window stretch capability permits the  simultane-
ous  stretching of a group of polygons, rectangles, and/or wires.
Object cut and merge capability allows selected objects to be cut
along  a  user-specified horizontal or vertical axis and overlap-
ping objects to be merged into a single object.   Group  and  Un-
group commands allow objects to be grouped into a new cell defin-
ition and an instance of a cell to be ungrouped.  The insides  of
instances  can  be  shown  or  hidden  on an individual basis.  A
cross-section   viewer   allows   the   designer   to    simulate
grow/deposit,  implant/diffuse,  and  etch  steps for mask layers
corresponding to the VLSI fabrication  process.  L-Edit  supports
CIF and GDSII file formats and directly produces the mask specif-
ication format required by MOSIS.  L-Edit 5.0 comes with  a  com-
plete  set of optimized layer, design rule, and device extraction
setups for MOSIS 2.0um and 1.2um  processes  and  Orbit/Foresight
2.0um, and 1.2um processes.


Standard Cell Automatic Layout Generation, L-Edit/SPR:

L-Edit/SPR is a set of placement and routing modules for automat-
ically  generating  layout.  contains  a standard cell placer and
router, a padframe generator, and a pad router. The Standard Cell
Placement  module  includes  a placement optimizer for optimizing
the size and performance of the circuit.  This is done by analyz-
ing  the  design  and  placing related cells next to one another,
thus shortening the  wires  in  between  them  and  reducing  the
overall  congestion  of the routing.  This optimizer uses a modi-
fied simulated annealing algorithm, and can significantly improve
a  design.   L-Edit/SPR's  channel  router  performs  the  wiring
between rows of cells.  It is a two-layer  channel  router  which
forms  connections  between  cells and runs wires to the edges of
the core.  It utilizes available space within cells when it needs
to  cross  a  row, thus reducing the need for inserting "spacers"
within the rows.  The signals which enter and leave a  chip  must
do  so  through  special cells called pads.  Pads usually provide
signal protection and buffering.  Pads are  arranged  in  a  ring
around  the  perimeter  of the core.  A Padframe Generator within
L-Edit/SPR can generate a padframe from  a  netlist,  or  from  a
dialog-box specification within L-Edit. When space exists between
pads, rails are automatically placed between the pads  to  ensure
continuity  around  the  padframe.  A Pad Router places a core of
logic within a padframe, and then wires  the  signals  which  run
between  the  core  and  the pads.  It also runs power and ground
rails to the appropriate pads in the ring.  It  can  be  executed
stand-alone,  or  together with the Padframe Generator and Place-
ment and Routing module.  L-Edit/SPR is fully-integrated into the
L-Edit  layout  editor  and  is activated by choosing a menu item
from within the L-Edit environment.


Design Rule Checker, L-Edit/DRC:

L-Edit/DRC is an on-line geometric design rule  checker  for  use
with L-Edit.  The DRC features user programmable DRC rules.   Use
of L-Edit's user-definable logical layer operations in  DRC  rule
specifications  allows  integrated  circuit  designers  to verify
their layout against the published geometric DRC constraints of a
silicon  foundry.   Rules  are one of seven basic types.  Minimum
width rules check for minimum  size  of  objects  (e.g.   minimum
transistor  width).  Exact width rules are for objects which must
be an exact size (e.g. contacts).  Minimum spacing rules ensure a
minimum  distance  between  two  objects  (e.g.  minimum distance
between two transistors).  The  minimum  surround  rule  verifies
that  a specified object is contained within another object (e.g.
metal contact surrounded by metal).  Overlap and Extension  rules
check  for  overlap and extension of intersection objects respec-
tively.  The design rule definitions used by  L-Edit/DRC  can  be
specified  using  any derived layer from L-Edit's Generate Layers
feature.  This capability greatly expands the set of rules  which
can  be  specified.   Intermediate layers can be temporarily gen-
erated using AND, OR, NOT, GROW, and SHRINK operations,  and  the
derived results can be utilized in a design rule definition.  The
derived layers are generated and disposed of automatically.   In-
cluded with the L-Edit DRC module are MOSIS and Orbit Semiconduc-
tor scalable CMOS design rules.  L-Edit/DRC  is  fully-integrated
into L-Edit the layout editor and is activated by choosing a menu
item from within the L-Edit environment.  The  design  rules  and
the  set of layers used by L-Edit/DRC are constructed using menus
and dialogs within L-Edit.  The DRC supports error reporting  via
a  text  file,  error objects, and error ports. A text file lists
all of the errors found upon running the DRC.  Error objects  and
error ports are placed on the layout at the coordinates where the
error was found.  With error ports, the text associated with  the
error  ports  represent a description of the particular rule that
was violated at a given location.  This text passes for the error
layer  can  be  set so that port text is only visible upon selec-
tion, and thus does not interfere with viewing the  layout.   The
DRC  Error Browser and Object Browser (Find Ports on Error Layer)
cycles through the DRC error ports one at a time, selecting  them
and optionally centering them on the screen.


General Device Extractor, L-Edit/Extract:

L-Edit/Extract is a generic device extractor that is  capable  of
recognizing  active  devices  including  BJTs,  diodes, GaAsFETs,
JFETs, MOSFETs and subcircuits.  It can also extract passive dev-
ices:  capacitors,  inductors  and  resistors.   In  addition, L-
Edit/Extract is process-independent.  This is accomplished by de-
fining  a series of connections which describe how the layers in-
teract electrically.  L-Edit/Extract is fully-integrated into the
L-Edit  layout  editor  and  is activated by choosing a menu item
from within the L-Edit environment.   The  extractor  definitions
used  by  L-Edit/Extract can be specified using any derived layer
from L-Edit's Generate Layers feature.  This  capability  greatly
expands  the  set  of rules which can be specified.  Intermediate
layers can be temporarily generated using AND, OR, and NOT opera-
tions,  and  the derived results can be utilized in an extraction
definition.  The derived layers are generated and disposed of au-
tomatically.   L-Edit/Extract  is  capable of extracting the most
common device parameters, including resistance, capacitance,  and
device  length,  width and area.  These parameters provide useful
information when verifying drive, fanout and other  circuit  per-
formance  characteristics.   The  extractor  will  also allow the
specification of  multiple  devices  with  the  same  recognition
layer,  but  differing pins.  The extractor will successfully ex-
tract these devices.  This is particularly useful  in  extracting
multi-source/drain  transistors and CCD elements.  L-Edit/Extract
creates a netlist file which contains  the  circuit  description.
This  netlist  is  in  industry-standard  SPICE  format (Berkeley
Spice, HSPICET, and PSpiceT), so that it can be used with a SPICE
simulator,  Tanner  Tools'  LVS,  or other tools which read SPICE
format netlists.


Layout vs. Schematic Netlist Comparator, LVS:

LVS is a netlist comparison program designed to compare  any  two
netlists  and  decide whether they describe the same circuit.  If
they do not, LVS assists in identifying and  correcting  ambigui-
ties.   LVS  can be used to determine whether a schematic circuit
matches a piece of layout, or whether  two  different  schematics
implement the same circuit.  LVS accepts standard SPICE-formatted
netlists (Berkeley Spice, HSPICET, and PSpiceT). Hierarchical  or
flat  netlists are accepted.  LVS is capable of identifying auto-
morph classes, or sets of elements or nodes which cannot be  dis-
tinguished  from  one another for some reason (such as devices in
parallel).  When two netlists are not equivalent, LVS can identi-
fy  unresolvable nodes and devices and assist in locating them on
the original schematic or layout.  LVS can  be  supplied  before-
hand  with  additional  information in order to resolve automorph
classes.  Sets  of  nodes  or  elements  can  be  pre-defined  as
equivalent.   LVS  has  a process called trial matching which at-
tempts to resolve automorph classes.  This process  involves  re-
peatedly  matching a pair of otherwise undistinquishable nodes or
elements, and then attempting to resolve the circuits again.   In
addition  to  using topological information (such as device types
or number of  connections)  to  compare  netlists,  LVS  can  use
parametric   values   such  as  resistance  and  capacitance,  or
geometric values such as area, length and width.  Comparison mar-
gins  can be defined to determine how different two values can be
while still comparing equivalently.  Different margins can be de-
fined for parametric and geometric comparisons.  LVS also handles
parallel collapsing of resistors, capacitors and MOSFETS,  series
collapsing  of  resistors  and capacitors, series substitution of
series-chain transistors, input of global node handling and Spice
netlist  support  with  parameters  automatically being passed to
subcircuits.

All programs are available for IBM PS/2 or  PC/AT  or  compatible
with  386  or higher processor, Sun/SPARC, HP-9000, and Macintosh
systems.  On the PC, L-Edit V5 can be operated as a  DOS  program
under  Windows  3.1  and IBM OS/2 2.0.  Layout database files are
fully compatible between all supported platforms.

James T. Lindauer
Tanner Research, Inc.        Ph:   818-792-3000
180 N. Vinedo Ave.           Fax:  818-792-0300
Pasadena, CA.  91107         

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