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FILENUMBER: 3015 BEGIN_KEYWORDS VHDL text gate arrays standard vhdl Navabi END_KEYWORDS DATE: july 1993 TITLE: Text on VHDL Analysis and Modeling of Digital Systems by Z. Navabi Text on VHDL Analysis and Modeling of Digital Systems by Z. Navabi (Contributed by Z. Navabi of Northeastern University) VHDL: ANALYSIS AND MODELING OF DIGITAL SYSTEMS Zainalabedin Navabi; McGraw-Hill 1993; ISBN# 0-07-046472-3; Under $40.00; Order Department 1-800-338-3987; VHDL: ANALYSIS AND MODELING OF DIGITAL SYSTEMS introduces VHDL for design, description, modeling, and simulation of hardware. This text includes syntax details and diagrams to clearly show the construct of the language and how it is used. Familiar hardware components are presented and the VHDL descriptions which correspond to these components are discussed. After the introduc- tory chapters, the main concepts of the language are presented from structural to behavioral. The last chapter wraps it all to- gether by discussing modeling and design of an eight-bit proces- sor. A solutions manual and a diskette that contains a run of all the book problems and solutions to the end-of-chapter problems is available. T A B L E O F C O N T E N T S CHAPTER 1..............................................1 1.1 Digital System Design Process......................2 1.1.1 Design Automation................................3 1.2 Hardware Description Languages.....................4 1.2.1 A Language for Behavioral Descriptions...........5 1.2.2 A Language for Describing Flow of Data...........7 1.2.3 A Language for Describing Netlists...............9 1.3 Hardware Simulation...............................10 1.3.1 Oblivious Simulation............................12 1.3.2 Event Driven Simulation.........................13 1.4 Hardware Synthesis................................15 1.5 Levels of Abstraction.............................16 1.6 Summary...........................................17 References.............................................18 PROBLEMS...............................................19 CHAPTER 2.............................................21 2.1 VHDL Initiation...................................21 2.2 Existing Languages................................22 2.2.1 AHPL............................................22 2.2.2 CDL.............................................23 2.2.3 CONLAN..........................................23 2.2.4 IDL.............................................23 2.2.5 ISPS............................................23 2.2.6 TEGAS...........................................24 2.2.7 TI-HDL..........................................24 2.2.8 ZEUS............................................24 2.3 VHDL Requirements.................................25 2.3.1 General Features................................25 2.3.2 Support for Design Hierarchy....................25 2.3.3 Library Support.................................27 2.3.4 Sequential Statement............................27 2.3.5 Generic Design..................................28 2.3.6 Type Declaration and Usage......................28 2.3.7 Use of Subprograms..............................29 2.3.8 Timing Control..................................29 2.3.9 Structural Specification........................30 2.4 The VHDL Language.................................30 2.5 A VHDL Based Design Process.......................31 2.6 Summary...........................................34 References.............................................35 PROBLEMS...............................................36 CHAPTER 3.............................................37 3.1 Basic Concepts....................................37 3.1.1 An Illustrative Example.........................39 3.1.2 Interface Description...........................41 3.1.3 Architectural Description.......................44 3.1.4 Subprograms.....................................50 3.1.5 VHDL Operators..................................51 3.2 Timing and Concurrency............................53 3.2.1 Objects and Classes.............................55 3.2.2 Signals and Variables...........................55 3.2.3 Signal Assignments..............................56 3.2.4 Concurrent and Sequential Assignments...........58 3.2.4.1 Concurrency....................................58 3.2.4.2 Events and Transactions.......................59 3.2.4.3 Delta Delay...................................62 3.2.4.4 Sequential Assignments........................65 3.3 Conventions and Syntax............................71 3.4 Summary...........................................72 References.............................................72 PROBLEMS...............................................74 CHAPTER 4.............................................78 4.1 Parts Library.....................................79 4.1.1 Inverter Model..................................79 4.1.2 NAND Gate Models................................82 4.2 Wiring of Primitives..............................84 4.2.1 Logic Design of Comparator.....................85 4.2.2 VHDL Description of bit_comparator.............87 4.3 Wiring Iterative Networks.........................93 4.3.1 Design of a Four Bit Comparator.................94 4.3.2 VHDL Description of a Four Bit Comparator.......95 4.4 Modeling a Test Bench............................101 4.4.1 VHDL Description of A Simple Test Bench........102 4.4.2 Simulation.....................................105 4.5 Binding Alternatives.............................107 4.6 Summary..........................................113 References............................................114 PROBLEMS..............................................115 CHAPTER 5............................................120 5.1 Definition and Usage of Subprograms..............121 5.1.1 A Functional Single Bit Comparator.............121 5.1.2 Using Procedures in a Test Bench...............123 5.1.3 Language Aspects of Subprograms................127 5.1.4 Utility Procedures.............................130 5.2 Packaging Parts and Utilities....................132 5.2.1 Packaging Components...........................132 5.2.2 Packaging Subprograms..........................134 5.3 Design Parametrization...........................137 5.3.1 Using Default Values...........................140 5.3.2 Using Fixed Values.............................141 5.3.3 Passing Generic Parameters.....................143 5.4 Design Configuration.............................149 5.4.1 A General Purpose Test Bench...................149 5.4.2 Configuring Nested Components..................154 5.4.3 An Eight Bit Register Example..................161 5.5 Design Libraries.................................169 5.6 Summary..........................................172 References............................................172 PROBLEMS..............................................174 CHAPTER 6............................................178 6.1 Type Declarations and Usage......................179 6.1.1 Enumeration Type for Multi-Value Logic.........179 6.1.1.1 Modeling a Four Value Inverter...............180 6.1.1.2 Modeling a Four Value NAND Gate..............182 6.1.1.3 Initial Values of Enumeration Types..........184 6.1.2 Using Real Numbers For Timing Calculations.....184 6.1.3 Physical Types and RC Timing...................186 6.1.4 Array Declarations.............................189 6.1.4.1 Initializing Multi-Dimensional Arrays........192 6.1.4.2 Non Integer Indexing.........................193 6.1.4.3 Unconstrained Arrays.........................194 6.1.5 File Type and External File I/O................198 6.2 Subprogram Parameter Types and Overloading.......201 6.3 Other Types and Type Related Issues..............212 6.3.1 Subtypes.......................................212 6.3.2 Record Types...................................214 6.3.3 Alias Declaration..............................215 6.4 Predefined Attributes............................217 6.4.1 Array Attributes...............................217 6.4.2 Type Attributes................................218 6.4.3 Signal Attributes..............................220 6.5 User-defined Attributes..........................225 6.6 Packaging Basic Utilities........................227 6.7 Summary..........................................230 References............................................231 PROBLEMS..............................................232 CHAPTER 7............................................236 7.1 Multiplexing and Data Selection..................237 7.1.1 General Multiplexing...........................238 7.1.2 Guarded Signal Assignments.....................243 7.1.3 Nesting Guarded Blocks.........................249 7.1.4 Resolving Between Several Driving Values.......253 7.1.4.1 Revisiting Multiplexer.......................255 7.1.4.2 Packaging Resolution Functions...............257 7.1.5 MOS Implementation of Multiplexer..............259 7.1.5.1 Delaying Disconnections......................264 7.1.5.2 A Recommendation.............................265 7.1.6 A General Multiplexer..........................266 7.2 State Machine Description........................268 7.2.1 A Sequence Detector............................268 7.2.2 Allowing Multiple Active States................271 7.2.3 Outputs of Mealy and Moore Machines............273 7.3 Open Collector Gates.............................274 7.4 A General Dataflow Circuit.......................280 7.6 Summary..........................................287 References............................................287 PROBLEMS..............................................289 CHAPTER 8............................................295 8.1 Process Statement................................296 8.1.1 Declarative Part of a Process..................296 8.1.2 Statement Part of a Process....................297 8.1.3 Sensitivity List...............................299 8.1.4 A First Process Example........................300 8.1.5 Syntax Details of Process Statements...........304 8.1.6 Behavioral Flow Control Constructs.............305 8.2 Assertion Statement..............................306 8.2.1 Sequential Use of Assertion Statements.........307 8.2.2 Concurrent Assertion Statements................309 8.3 Sequential Wait Statements.......................312 8.3.1 A Behavioral State Machine.....................313 8.3.2 Two Phase Clocking.............................316 8.3.3 Implementing Handshaking.......................317 8.4 Formatted ASCII I/O Operations...................323 8.4.1 Basic Screen Output............................323 8.4.2 A Display Procedure............................325 8.4.3 Simulation Report..............................326 8.5 MSI Based Design.................................331 8.5.1 Top Level Partitioning.........................331 8.5.2 Description of Components......................333 8.5.3 Design Implementation..........................336 8.6 Summary..........................................340 References............................................341 PROBLEMS..............................................342 CHAPTER 9............................................350 9.1 Defining a Comprehensive Example.................351 9.2 Parwan CPU.......................................352 9.2.1 Memory Organization of Parwan..................352 9.2.2 Instruction Set................................353 9.2.3 Instruction Format.............................355 9.2.3.1 Full Address Instructions....................356 9.2.3.2 Page Address Instructions....................357 9.2.3.3 Non Address Instructions.....................358 9.2.3.4 Indirect Addressing in Parwan................359 9.2.4 Programming in Parwan Assembly.................359 9.3 Behavioral Description of Parwan.................360 9.3.1 Timing and Clocking............................360 9.3.2 Packages.......................................361 9.3.2.1 Par_utilities Package........................361 9.3.2.2 Par_parameters Package.......................364 9.3.3 Interface Description of Parwan................364 9.3.4 Parwan Behavioral Architecture.................365 9.4 Parwan Bussing Structure.........................372 9.4.1 Interconnection of Components..................373 9.4.2 Global View of Parwan Components...............374 9.4.3 Instruction Execution..........................374 9.5 Dataflow Description of Parwan...................376 9.5.1 Data and Control Partitioning..................376 9.5.2 Timing of Data and Control Events..............378 9.5.3 General Description Methodology................379 9.5.4 Description of Components......................379 9.5.4.1 Arithmetic Logic Unit........................379 9.5.4.2 Shifter Unit.................................382 9.5.4.3 Status Register Unit.........................384 9.5.4.4 Accumulator..................................386 9.5.4.5 Instruction Register.........................387 9.5.4.6 Program Counter..............................388 9.5.4.7 Memory Address Register......................390 9.5.5 Data Section of Parwan.........................392 9.5.6 Control Section of Parwan......................397 9.5.7 Wiring Data and Control Sections...............412 9.6 A Test Bench for Parwan..........................414 9.7 Summary..........................................418 References............................................418 PROBLEMS..............................................419 APPENDIX A...........................................424 APPENDIX B...........................................431 B.1 A Session of the VDS VHDL Environment............432 B.2 A Session of the V-System/Windows VHDL Environment...........................................437 B.3 A Session of the VLK VHDL Environment............440 B.4 A Session of the VDS VHDL Environment............444 APPENDIX C...........................................447 C.1 74LS85 4-Bit Magnitude Comparator ...............448 C.2 74LS157 Quadruple 2-Line to 1-Line Multiplexer ..449 C.3 74LS163 Synchronous 4-Bit Counter ...............450 C.4 74LS283 4-Bit Binary Full Adder..................451 C.5 74LS373 Octal D-Type Transparent Latches.........451 C.6 74LS377 Octal D-Type Flip-Flops .................452 C.7 74LS299 Universal Shift-Register.................453 C.8 74LS541 Tranceiver...............................453 APPENDIX D...........................................455 D.1 Parwan Behavioral Description....................455 D.2 Controller of Parwan Dataflow Description........459 APPENDIX E...........................................466 APPENDIX F...........................................483 F.1 STANDARD Package.................................483 F.2 TEXTIO Package...................................484

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