MICROELECTRONIC SYSTEMS NEWS



FILENUMBER: 3018
BEGIN_KEYWORDS
software mosis xilinx tanner gate arrays standard cell vhdl
END_KEYWORDS
DATE: july 1993
TITLE: Software for Computer-Aided Logical Design Text by Hill


Software for Computer-Aided Logical Design Text by Hill

(Contributed by Fred Hill of the University of Arizona)


From John Wiley & Sons advertisement:

COMPUTER AIDED LOGICAL DESIGN WITH EMPHASIS ON VLSI by Fred  Hill
is now in its fourth edition.  New features include:

* The first text to bridge the gap between VLSI design and  logi-
  cal design.

* Design problems are now included to support the design require-
  ments established by ABET.

* NMOS and CMOS circuits are covered in detail.

* New problem sets are provided at the end of every chapter.

* Includes coverage of programmable  logic  arrays,  programmable
  logic devices, field-programmable gate arrays and standard cell
  design.

* New sections on register transfer level descriptions.

* Stresses what computer aided logic design tools can do.

The new edition maintains the strengths that have  proven  effec-
tive through three previous editions:

* Noted for its careful introduction to Boolean algebra, Karnaugh
  maps and sequential circuits.

* Covers system level implications of circuit properties.

* Considers both behavior and structure in the design process.

* Uses design methodologies applicable to real-world scale designs.

A solutions manual is available for instructors.  Also,  software
to support the text can be obtained directly from the author.

To order from John Wiley & Sons, call (212)-850-6000.


From Fred Hill:

This document is precipitated primarily by references to software
support  in  advertising  for "Computer Aided Logical Design with
emphasis on VLSI."  The most important point to be made is: don't
judge  the  book  on  the basis of potential supporting software.
The book includes careful treatment of the fundamentals of  logi-
cal  design as well as topics in the area of digital VLSI design,
not assembled in any other textbook.  Obtain  a  desk/examination
copy of the book before you make your decision.

Clearly one should not expect  non-commercial  software  to  com-
pletely  support  a  laboratory course in logical or VLSI design.
While this author argues for hardware compilation from AHPL as  a
more natural design entry than graphic design capture, the latter
remains an essential component of an undergraduate logical design
laboratory.  I make no attempt to supply a schematic capture tool
or a gate level simulator.  The book is not tied directly to  any
set of tools.  A course using "Computer Aided Logical Design with
emphasis on VLSI" may be supported by a laboratory  of  tools  of
the instructors choosing.

The  advertised software  becomes  applicable when a course using
the  above  referenced  book  reaches Chapter 11.  The clock mode
function level simulator HPSIM2 supports this chapter as well  as
the  authors  other book, "Digital Systems: Hardware Organization
and Design."  The hardware compiler program HPCOM and AENT, which
translates  HPCOM output to EDIF 1.0 (electronic data interchange
format), are natural elements of a VLSI design laboratory.  A ma-
jor  goal has been to make the output of AENT compatible with the
input net-list and libraries utilized by the  standard  cell  au-
tomatic place and route routine associated with L-Edit.  Informa-
tion on L-Edit can be obtained from   Tanner  Research  Inc.  444
North  Altadena  Drive,  Pasadena,  California  91107 ((818) 795-
1696).  It is intended that the combination of  HPCOM,  AENT  and
L-Edit provide a direct translation of AHPL to a MOSIS compatible
standard cell layout, but I offer no guarantee that gaps will not
arise  as  the various programs progress from version to version.
Such a realization of an AHPL description could then be simulated
at  the  gate level with capacitance values back annotated to the
net-list by a Tanner product.

THE FUTURE:  Although  HPSIM  and  HPCOM  have  been  static  for
several  years,  some  enhancements are in store for the near fu-
ture.  Among these are optional execution of combinational  logic
unit  descriptions  by HPSIM and optional generation of a minimal
memory element control unit by HPCOM.  We are also in the process
of developing an AENT like program which will provide for realiz-
ing AHPL descriptions as FPGAs.  I will keep those,  who  provide
EMAIL addresses, updated of these developments.

The tool package consisting of HPSIM2, HPCOM, and AENT is  avail-
able  for MSDOS (IBM PC compatible) computers.  A fourth program,
SUBGRAPH, which generates a  partial  logic  block  diagram  from
HPCOM output, and one or more possibly helpful public domain pro-
grams are included on  the  distribution  disk  free  of  charge.
Although  HPSIM2  is available on one or two other platforms, The
complete package is  supported  only  for  MSDOS  at  this  time.
Although  the  user  manual  has  been updated, versions of HPSIM
which may be in use at various Universities, do not  differ  from
the current version.

The price for the three program package (HPSIM, HPCOM, and  AENT)
including  a  comprehensive  hard  copy user manual is $150.  The
price for the MSDOS version of HPSIM2 only is $100.  Checks (pay-
able  to  the University of Arizona) or purchase orders should be
sent to:

               Dr. Fredrick J. Hill
               Department of Electrical and Computer Engineering
               University of Arizona
               Tucson, Arizona 85721
               hill@ece.arizona.edu

Advance payment is not required, but this  method  is  most  con-
venient.   Instructors  are  authorized  to  make  copies  of the
software and user manual for use by students in their classes.

The following paragraphs should be of interest to  all  who  make
use  of  Xilinx  2000  and  3000  series  logic cell arrays in an
academic environment.  It should be  of  particular  interest  to
those  Xilinx users who also make use of the Tanner Research pro-
duct, NetTran or can otherwise translate  an  EDIF  1.1  net-list
into Xilinx xxx.xnf format.

For several years I have made available a small set  of  software
products  which  support  the hardware description language AHPL.
In addition to the function level simulator and hardware compiler
HPCOM,  I distribute a program, AENT, which will translate a net-
list to to EDIF 1.1 format.  The EDIF net-list is then  typically
submitted  to  NetTran,  with the output used to drive the Tanner
L-Edit standard cell place and route program.  The  final  result
is  a  CIF realization of the original AHPL description which can
be sent to MOSIS for fabrication.

In conjunction with Xilinx logic cell array  realization  in  our
undergraduate   computer   aided  logical  design  laboratory  we
discovered that the same version of AENT could  be  used  as  the
first step in generation of an XNF format net-list, acceptable to
the Xilinx tool set.  Tanner NetTran will also translate the EDIF
1.1 format from AENT to XNF format.  AENT allows a sufficient set
of user options to support  separate  styles  (particularly  with
respect  to  I/O pins) for logic cell array realization and stan-
dard cell fabrication.

As always, the  advantage  of  a  hardware  description  language
front-end  is that schematic capture is bypassed.  Schematic cap-
ture may be helpful when the design process  draws  from  a  very
large  library  of  complex parts or cells.  Adaptation to Xilinx
cells always takes place further downstream in the synthesis pro-
cess, under control of Xilinx XACT software.  Nothing is lost, if
the most generic possible XNF net-list (AND, OR,  and  NOT  gates
with  D flip-flops) is submitted to XACT.  This format is readily
produced by HPCOM and AENT.    A  similar  synthesis  process  is
available  for  VHDL, but for this application VHDL offers no ad-
vantages over the much simpler AHPL.

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