MICROELECTRONIC SYSTEMS NEWS



FILENUMBER: 443
BEGIN_KEYWORDS
Text IDDQ Testing CMOS VLSI Rajsuman
END_KEYWORDS
DATE: february 1995
TITLE: Text on IDDQ Testing for CMOS VLSI by Rajsuman


Text on IDDQ Testing for CMOS VLSI by Rajsuman

(Contributed by Rochit Rajsuman of Case Western Reserve University)

"IDDQ Testing for CMOS VLSI" by Rochit Rajsuman
covers Iddq testing,
a highly effective way to reduce the cost of testing and increase
the reliability of integrated circuits. Based on monitoring the quiescent supply
current, Iddq testing detects the physical defects in ICs and also senses the
parasitic drifts that may eventually cause a device to fail. This comprehensive new
book provides unsurpassed coverage of Iddq testing's fundamental concept and shows
you how to start saving money immediately.

The text includes detailed discussion of the correlation between physical defects
and logical faults, and shows you how Iddq testing detects these defects. Iddq
Testing for CMOS VLSI gives you instant access to valuable information on:

** Test generation for Iddq testing
** Use of stuck-at and random vectors for Iddq testing
** Use of Iddq testing in factory production lines
** Cost-benefit analysis
** Instrumentation issues
** Off-chip and on-chip current sensors
** ATE interface
** Case studies with memories and microprocessors
** Proposed IEEE QTAG standard

The book provides planning guidelines and optimization methods and is
illustrated with numerous examples ranging from simple circuits to extensive case
studies. It presents the latest Iddq testing techniques and demonstrates how
to perform cost-benefit analysis that quantify savings. "Iddq Testing for CMOS
VLSI" is an invaluable reference for designers, test engineers, managers and R&D
departments in the semiconductor IC industry.

CONTENTS:
Introduction: Physical defects and bridging faults in CMOS ICs, fault models for
CMOS VLSI circuits, physical defects and bridging faults.

Introduction to Current Testing: Basic concept of Iddq testing, estimation of fault
free current, Iddq threshold specification, capabilities of Iddq testing and design
rules.

Test Generation for Iddq Testing: Use of stuck-at test sets, random test vectors in
Iddq testing, dedicated test generation for Iddq testing, user's specified test sets,
comparison.

Manufacturability and Use in Production: Iddq testable chips, Iddq test criteria,
use of Iddq testing in a production line, cost-benefit analysis.

Current Sensing Techniques: Off-chip current sensing techniques, on-chip current
sensors, integration with existing BIST, proposed QTAG standard, ATE requirements.

Case Studies with Iddq Testing: Study on random access memories, study on micro-
programmed processor.

Summary and Suggestions: Summary, suggestion and future direction.

Hardcover. 6" x 9". Approx. 200 pages. 
Available October 1994.
Order Book SW3726                       $65.00


To order the book:


		   Artech House Inc., 
		   685 Canton Street
		   Norwood, MA 02062
           Phone 1-800-225-9977 or 617-769-9750, ext. 4002
           Fax 617-769-6334
           email artech@world.std.com
           For gopher world.std.com - select Book Sellers 

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