MICROELECTRONIC SYSTEMS NEWS



FILENUMBER: 451
BEGIN_KEYWORDS
ALLIANCE VHDL Synthesis Software
END_KEYWORDS
DATE: april 1995
TITLE: ALLIANCE -- VHDL Synthesis Software for Free


ALLIANCE -- VHDL Synthesis Software for Free

(Contributed by Steve Dao of Rose-Hulman Inst.)


The CAD-VLSI team at Pierre et Marie Curie University has released version 2.0 of
the ALLIANCE VLSI CAD system.  The release  still supports the top-down approach of
Mead-Conway and provides two  design paths to produce a custom VLSI chip.  Each path
consists of  five distinct parts with the associated tools:
 
     behavioral description at the VHDL level:
     VHDL compiler
     genpath, test pattern generator
     asimut, functional simulator

     structural view capture.
     genlib, module generator
     asimut, structural simulator

     physical layout
     genlib, cell placement procedural generator
     scr, standard cell place and route tool
     ring, core to pads router

     verification
     versatil, hierarchical design rule checker
     lynx, layout to netlist extractor
     desb, functional abstractor to generator behavioral description
     proof, formal proof analyzer to compare resulting behavior
     against initial specifications
     lvx, layout versus schematic gate netlist comparator
     s2r, symbolic layout to micron translator

     test and coverage evaluation
     GenRad Hifault, fault simulator

Release 2.0 provides additional support for the logic synthesis stage  
which can replace the structural view as an alternative design path.   
The logic synthesis tools include:

     logic, gate netlist generator from VHDL behavioral description
     syf, finite state machine synthesizer
     netoptim, netlist timing optimizer

The extensive standard cell libraries use a symbolic layout  
approach to achieve process independence and easy portability from  
one technology to the next.  Release 2.0 introduces the following new  
cell libraries and tools:

     dplib, standard cell library for data path design
     fpgen, data-path compiler for high performance and high density
     circuits
     dpr, data-path router
     rage, static RAM generator
     grog, high speed ROM generator
     rsa, fast adder generator
     bsg, barrel-shift generator
     amg, pipelined multiplier generator
     rfg, multi-ports register file generator

Additional features in 2.0 include:

     graal, symbolic layout editor with MOTIF interface
     genview, procedural layout debugger for custom block
     development
     binaries for SPARC running SunOS 4.1.1, Sun 3 running SunOS
     4.1.1, DEC 5100
     running Ultrix, and 386/486 PC running Linux 1.0.9 or higher
     small program to automatically generate new technology files
     compatible with COMPASS and CADENCE place and route tools

     three tutorials featuring chip designs of varying complexity are
     available to illustrate the different design tools:
     addaccu, design of adder/accumulator chip (about 500
     transistors)
     amd2901, design of the 4-bit AMD2901 processor (3000 about
     transistors)
     dlx, design of the 32-bit DLX microprocessor from Hennessy and
     Patterson (30000 transistors)

ALLIANCE 2.0 has been thoroughly tested and proven by hundreds  
of users.  Simple processors with 2000 transistors to complex  
superscaler microprocessors with 800,000 transistors have been  
successfully designed and validated using ALLIANCE.  Therefore,
ALLIANCE provides the sophistication and power of a commercial CAD  
system without the
complexity.

ALLIANCE 2.0 is available for free via anonymous ftp from  
ftp.ibp.fr in directory /ipb/softs/masi/alliance.  The log in  
password is the user's e-mail address.  The main file is
alliance-2.0.tar.Z.  Source files written in C are also available.   
Complete documentation in the form of on-line man pages or printed  
manuals is included.
   
  

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