MICROELECTRONIC SYSTEMS NEWS



FILENUMBER: 503
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student design experiment european
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DATE: january 1994
TITLE: European-wide Student Design Experiment

European-wide Student Design Experiment

(Contributed by Einar Aas of the Norwegian Institute of Technology)


1. INTRODUCTION

The paper "Student Design Experiments - Lessons Learned in Design and 
verification", presented at the EUROCHIP Workshop on VLSI Design Training
30 September 1993, describes the results of small scale design experiments
performed with 41 students at the Norwegian Institute of Technology.
Another relevant paper is : Aas et.al. "Quantifying Design Quality through
Design Experiments", to appear in IEEE D&T Magazine early 1994.

These experiments may be repeated at other universities and colleges.
This invitation has already been sent to the majority of the European
universities through the EUROCHIP channel.

Below we describe briefly the motivation for an orchestrated event
on design experiments, the actual experimental setup, tasks to be completed,
and information on how to participate.

2. MOTIVATION

The motivation for participating in this design experiment depends on
one's position:

  Students:     Feedback on own ability as designer in terms of optimality
                of design, errors made, and own verification strategy to 
                detect and correct design errors. Time spent is also recorded.
                You have a chance to compare yourself against other European
                students, while preserving own anonymity.

  Supervisors:  Study the effect of teaching design methodology and techniques,
                and get an overview of class performance. Get access to data
                on similar experiments in Europe. Eventually compare
                your students against other European students.

  Myself(Aas):  Receive and analyze results from the experiments, and prepare
                and present statistical results on parameters of interest. Of
                particular interest is designer error rates, design error types,
                and the efficacy of various verification strategies.

3. DESIGN EXPERIMENT SETUP

The design experiments rely on traditional manual logic optimisation
principles, and the use of standard CAD tools like schematics capture and logic
simulation. This is done because most industrial designs still use these
methods, and because every VLSI design student should be capable of
performing manually optimized designs also. Automatic synthesis will be done at
our university for overall comparison.


The setup is briefly as follows:

Given an Espresso optimized PLA (i.e. a set of implicants for the ON-set of
the function) to be redesigned as a multilevel circuit, and a limited set of
library gates to be used (NOT, 2 & 3 input NAND,NOR).

        DO manual synthesis with low gate cost as objective.

        CAPTURE the design by schematic entry.

        VERIFY functionality by logic simulation. Correct
        design errors detected, and resimulate. Do this 3
        times with different "test" pattern sets, as described below.
        
Verification strategies:

  1. Own test set: Derive a test set you think will exercise the given
                   function.

  2. A 100% stuck-at test set (for the PLA).

  3. A rather large set of pseudorandom patterns.

After each of these verifications (including corrections to have the design 
pass all patterns), run a complete set of test patterns, and correct if needed
to obtain a functionally correct circuit.

During these experiments, data of interest shall be recorded by each student:
Design time, no. and type of design errors found, gate cost, a computed
measure for the design effort (no. of atomic design operations) etc.
The time required is approximately 16 hours average per student, while
individual variation was large: between 7 and 28 hours.

4. TASKS FOR THE SUPERVISOR

The supervisor organises the experiments according to detailed instructions,
records the data of interest, and transmits the data by Email to Aas. He/she
ensures anonymity of each student to avoid embellishing the results, and
takes responsibility for a fair and proper execution of the experiments.

The students need access to a schematic editor (or netlist compiler), 
and a logic simulator.
You have to set up a testbench with the PLA as the correct function, and a
comparator to flag deviations between expected and actual response.
Stimuli will be provided by me, in addition to these devised by the students.

5. HOW TO PARTICIPATE

If you want your students to participate in this experiment, simply fill in and
send the request below to me by Email , preferably before
1. November. You will receive instructions as soon as I have read your request.
The deadline for return of the result is 1. June, and you will receive a
copy of the overall analysis of the experiments as soon as they are processed.


If you have any questions, please feel free to contact me by Email:

                


           Professor Einar J. Aas
           The Norwegian Institute of Technology
           Faculty of Electrical Eng. & Comp. Science
           N-7034 Trondheim-NTH
           NORWAY

           Phone: +47 73594317    Fax: +47 73591441
           Email: Einar.Aas@delab.sintef.no

           Home phone: +47 73522120

------------------------------------------------------------------------------
REQUEST FOR PARTICIPATION IN EUROPEAN DESIGN EXPERIMENTS ORGANIZED BY E.J. AAS
------------------------------------------------------------------------------
NAME OF SUPERVISOR:                                       DATE:
INSTITUTION:
EMAIL:
FAX:
POSTAL ADDRESS:

EXPECTED NO. OF STUDENTS:
DESIGN TOOLS TO BE USED: SCEMATIC ENTRY OR NETLIST INPUT:
                         LOGIC SIMULATOR:
PART OF COURSE (OR STAND ALONE PROJECT):
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