MICROELECTRONIC SYSTEMS NEWS



FILENUMBER: 511
BEGIN_KEYWORDS
VERIFICATION/SYNTHESIS SOFTWARE 
END_KEYWORDS
DATE: april 1996
TITLE: Verification/Synthesis Software Available



Verification/Synthesis Software Available

(Contributed by  Sunil Khatri of U. C. Berkeley)

Verification Interacting with Synthesis (VIS) is a software
package that is now available.  VIS has been developed through the 
combined efforts of the UC Berkeley and UC Boulder CAD groups.  
With this release, the HSIS tool from UC Berkeley is no longer 
being supported.

VIS provides the following features: 

- Fast simulation of logic circuits 
- Formal "implementation" verification of combinational and sequential
  circuits
- Formal "design" verification using fair CTL model checking and
  language emptiness 
- Logic synthesis via a path to SIS 

VIS is available through anonymous ftp at:

	VIS FTP 

The best way to get VIS is to follow the instructions on the VIS
homepage at: 

	VIS WWW 

You can even execute a trial run of VIS from this page.

A Verilog front end, vl2mv, is also provided, which compiles a subset
of Verilog into the intermediate format BLIF-MV read by VIS.

Extensive documentation is provided with the release.  A new user is
recommended to read the "VIS User's Manual" as a good way to get an
introduction to VIS, CTL Model Checking, fairness constraints, the
general philosophy behind VIS, and writing Verilog for VIS.  There is
also HTML-based user and programmer documentation that is not part of
the distribution, but is accessible on the VIS homepage.

VIS has been tested on the following machines:

- DEC (MIPS Ultrix V4.4 and Alpha OSF/1 V3.2)
- HP (Snake HP-UX)
- Sun4 (SunOS4.1.1 and Solaris 5.4)
- IBM PC 486 and Pentium (Linux 1.3.20)

If you would like to be added to the VIS users mailing list, 
please send mail to vis@ic.eecs.berkeley.edu indicating this.

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