MICROELECTRONIC SYSTEMS NEWS



FILENUMBER: 523
BEGIN_KEYWORDS
Intellectual Property Reusable Logic Cores
END_KEYWORDS
DATE: september 1996
TITLE: Intellectual Property as Reusable Logic Cores


Intellectual Property as Reusable Logic Cores

(Adapted from LSI Logic, TDF, Altera and Xilinx Press Releases)

Designers who are developing ASICs with more than a million gates
in  only  a  few  months are increasingly turning to intellectual
property building blocks or reusable  cores  to  achieve  complex
functionality  quickly.   Several  ASIC  and  FPGA  vendors offer
industry-standard functions  such  as  CPUs,  Ethernet  and  MPEG
cores,  as  well  as  associated  protocols and algorithms. Logic
designers achieve product differentiation by the way they develop
proprietary functions around the cores and system software.

In addition to the established program of offerings from LSI Log-
ic,  a  new  company,  Technical Data Freeway (TDF) supplies syn-
thesizable VHDL source code.  Prices are generally set  at  about
one-third  of  the  actual  development  cost,  saving the system
designer significant engineering costs and reducing the  time  to
market by several months.

For additional information, access:

LSI Logic WWW

TDF WWW

Altera Corporation offers a collection  of  common  megafunctions
that   have   been   designed expressly for Altera's programmable
logic devices. MegaCore functions are  pre-verified  designs  for
complex system-level building blocks such as microprocessors, mi-
crocontrollers, DSP engines, FIFOs, and  other memory  functions.
Altera  also  supports its Megafunction Partners Program in which
third-party designers contribute intellectual  property  building
blocks. In addition, Altera  has developed its new OpenCore tech-
nology, which allows engineers to  integrate  MegaCore  functions
for evaluation purposes prior to actually  licensing  them.

Xilinx  offers  pre-implemented   and   fully   verified  drop-in
modules  for  its  line of FPGAs.  As  a  result,  designers  can
dramatically  cut development  time, significantly reduce  design
risk,  and  have  access  to the best performance and lowest com-
ponent cost available.

For additional information, access:

Altera WWW

Xilinx WWW



 

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