MICROELECTRONIC SYSTEMS NEWS



FILENUMBER: 6015
BEGIN_KEYWORDS
mosis cadence capfast mentor graphics
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DATE: april 1994
TITLE: MOSIS Design Kits for Cadence and Mentor

MOSIS Design Kits for Cadence and Mentor

(Contributed by Dan Johnson of Advanced Microelectronics)

Advanced Microelectronics (AuE) is teaming with SanCAD and Phase Three Logic 
to assemble design kits targeted for the MOSIS foundry service. 
We will also be offering design kits for the Cadence OPUS environment 
and the Mentor Falcon Framework. The Cadence design kit is about 95% complete 
and the UNIX bundle is about 80% complete. 
Here is a brief summary of the proposed design kit bundles:

1. Generic UNIX Bundle
    - Phase III CAPFAST schematics
    - SanCAD Mobius circuit simulator
    - Verilog logic models w/ min,typ,max timing
    - Hspice/SanCAD netlists for all cells
    - AueMagic 6.5, layout editor
    - Updated Magic technology file for current MOSIS processes
    - GDSII stream files for all cells

2. Cadence Bundle
    - OPUS Composer schematics
    - Verilog logic models w/ min,typ,max timing
    - Hspice netlists for all cells
    - An OPUS technology file for selected MOSIS processes.
    - Preview router abstracts
    - Cell layouts compatible with ALE
    - Hspice netlists for all cells

3. Mentor Bundle
    - Schematics compatible with Design Architect
    - Quicksim logic models w/ min,typ,max timing
    - Hspice netlists for all cells
    - Interfaces to the Mentor routing and layout tools

4. EDIF Bundle
    - Symbols, schematics, and layouts in EDIF 2.0 format
    - SanCAD Mobius circuit simulator
    - Verilog logic models w/ min,typ,max timing
    - Hspice/SanCAD netlists for all cells

We have not determined final pricing yet but hope to be ready with an
announcement by the end of March. Please contact Dan Johnson (danj@aue.com)
if you have any additional questions.

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