MICROELECTRONIC SYSTEMS NEWS
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Proceedings Workshop Rapid System Prototyping
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DATE: july 1994
TITLE: Proceedings of IEEE Workshop on Rapid System Prototyping
Proceedings of IEEE Workshop on Rapid System Prototyping
(Contributed by Roderick McConnell of IRISA, France)
IEEE INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING
June 21-23, 1994, Grenoble, France
1. This year the workshop gathered 41 participants from 14 coun-
tries, with a shared interest in techniques for rapid systems
prototyping i.e. going quickly from an idea (specification) to a
working system (implementation). Notably sparse were discussions
on theory & proofs. The workshop was also unique in that, with a
relatively small group of participants, it also gathered practi-
tioners from both software-systems and hardware-systems develop-
ment. One of the organizers of the workshop emphasized that it
was important to have both software and hardware people SIT IN
THE SAME ROOM - that way, one could hope to have at least some
cross-fertilization (my experience is that interaction between
the two camps is rare).
The majority of the presentations were nevertheless concerned
with hardware: 14 out of 21 (if one includes those on HW/SW
codesign among the hardware group). This probably reflects more
than anything the relative maturity of software tools for
hardware design; software tools for software are still pretty
new, and hardware tools for software design don't exist yet.
What follows is a summary of three themes which interested me
during the workshop: the use of FPGA's for prototyping; model-
ing periodic processing (including my presentation); and manage-
ment techniques for prototyping. It goes without saying that
there were lots of other themes.
2. Most of the hardware presented, was at least partly done using
FPGA's. While this is probably somewhat typical of University
projets, I think it also reflects the possibilties of solving
"real" problems using programmable circuits. For example, the
presentation of David Andrews from the University of Arkansas,
"Rapid Prototype of an SIMD Processor Array (using FPGA's)",
talked of software development before first silicon, using a re-
duced array of processors programmed into some Xilinx 4000-series
chips. This is not a new idea, but I had the impression that
this time it worked (I compare it to an effort at AT&T, using a
previous generation of Xilinx: they needed so many Xilinx, that
by the time everything was partitioned & programmed and the
boards wired, first silicon was ready).
Likewise, Paul Fiore from Lockheed Sanders (to become just
"Lockheed" some day, I imagine) gave an example of using the Ap-
tix Field-Programmable Circuit Board to rapidly prototype a whole
system. Instead of re-wrapping a wire-wrap board (or cutting the
traces of a PCB!), they just re-programmed the routing circuit.
This allowed them to fix errors, but perhaps just as important,
this allowed them to start using the system with a standard
memory circuit, and then change components (and pinouts) when a
low-power version became available. It should be pointed out
that programmable circuits and circuit boards are particularly
interesting for prototyping low-speed applications such as low-
power (for high-speed applications, they should be used with
care). I'll come back to this presentation, "Rapid Development
of Signal Processors and the RASSP Program", when I mention the
RASSP program.
3. There were four presentations which were addressed exclusively
at periodic applications (read high-throughput DSP). The advan-
tage of periodicity, is that one knows in advance exactly which
tasks must be done when. This forms the basis for Synchronous
Data Flow, and for its extension to a hierarchical form in
Cyclo-static Data Flow. Apparently there are as yet no defini-
tive references to Cyclo-static, but the presentation entitled
"Geometric Parallelism and Cyclo-Static Data Flow in Grape-II" by
Rudy Lauwereins from KU Leuven talked about it.
Rudy's presentation was complemented by a demo using Grape-II, a
Compact Disc decoder and equalizer running in real time. Grape-
II is a programming environment of the same genre as Ptolemy (a
competitor, as Rudy put it, 'though both are given away for
free), targeted at code for multi-processor programmable systems.
The systems-level partitioning and scheduling was handled by
Grape, while the operations were programmed in 'C', and executed
on a multi-processor 'C40 board. The resulting system handled
both left and right channels of the CD in real time. As usual,
there were some unexpected technical difficulties with the demo -
the difficulties didn't delay completion by much, but indicated
for me the maturity of the Grape-II system. In fact, the folks
from K.U. Leuven had kept only source code as a backup, and used
the Grape-II compiler to redo the partitioning and scheduling on
the spot, rather than having kept a backup copy of the final exe-
cutable.
My impression ('though shared by others) is that Grape-II has
just the right mix of capability and small size, to be an in-
teresting software package for people in the domain. And think-
ing of domains, a nice advantage of Grape vis a vis Ptolemy, is
that Grape automatically chooses the domain depending on the
operator, whether it be static (or Cyclo-static) or dynamic
(data-dependent). Apparently ISI plans to bring it out as a pro-
duct under the name Virtuoso Synchro.
4. The last of the themes that I'll write about was how to organ-
izate a project for rapid prototyping. The keynote speaker, Mark
Richards, presented one approach, the RASSP projet: "The Rapid
Prototyping of Application-Specific Signal Processors (RASSP)
Program: Overview and Status". RASSP is a United States Depart-
ment of Defense program to try and speed up prototyping. I ima-
gine that the DoD is one of the parties most interested in rapid
prototyping, as defense equipment is rarely produced in large
enough quantities to amortize high development costs, and pro-
jects are typically constrained by performance (hence the desire
to see if that "cutting-edge" processor or system functions, at
least as a prototype). There were two things I particularly
liked about RASSP: first, it uses the idea of "model-year"
demonstrators, a series of throw-away demonstrators throughout a
project to let the users try out the equipment (and to let the
designers see what does and doesn't work); second, it includes a
plan to finance getting the ideas into the Universities, so that
engineers can learn about RASSP before getting into industry.
Paul Fiori also talked about RASSP, but his presentation more
than anything showed why one needs such a program. He described
the rapid prototyping environment at Lockheed Sanders, which con-
sists of reputable tools: Matlab for algorithm development; Xi-
linx "apr" and "xact" for the FPGA's; ViewLogix for the simula-
tion; and a H.P. pattern generator to generate the test vectors
for the target hardware. The problem: each of these tools re-
quires a fairly sophisticated user (i.e. months or years of prac-
tice), not only in terms of understanding of the problem to be
solved, but also in terms of the "stupid details" of using each
tool. If RASSP can provide a framework to integrate at least
some of these tools or their equivalents, that in itself would
help engineers, at least in getting started quickly. My personal
experience, based on a project that included the same sort of
components (CPU's, and programmable and regular components on a
wire-wrap board), is that for someone who knows the different
tools, using a specialized tool for the task at hand makes
development and debugging much faster. If the time between a new
algorithm and modifying the hardware is short (measured in
minutes or hours), one has the chance to "play" with different
algorithms; this in turn lets one optimize the algorithm and the
hardware at the same time. On the other hand, getting the in-
teractions between the tools at least semi-automated takes time,
and learning to use a new tool can be a painful task.
Another presentation on project-level approaches, but this time
exclusively for software development, was given by Richard Estra-
da of Bolt Beranek and Newman: "Dynamic Analysis and Replanning
Tool (DART): a Case Study of Accelerated Evolutionary Develop-
ment". If "Accelerated Evolution" seems like an oxymoron, it
might be because the comparision is to current DoD practice,
where a software package takes typically 5.5 to 9 years to
develop (according to R. Estrada). As with RASSP, part of the
proposed approach is to provide intermediary models to the user
every few months (though part of the hope with software is to
re-use, rather than throw away as with RASSP). The success story
used to justify the approach, was a logistics package developed
for the Gulf War in a span of 10 weeks! Another interesting idea
was the way in which intermediary software is distributed for
on-site demos: either by putting it on disk and carrying it, or
by transfer across the electronic net. A nifty debugging idea:
send the software over, install and compile it, and then use X-
windows across the net to debug it from the originating site.
5. In conclusion, some general observations about this & that.
The conference site, the Grand Hotel de Paris at Villard de Lans,
was a nice choice: a resort hotel, in the mountains and surround-
ed by hiking trails. The food was of quality, however their
selection of red wine was disappionting (un vin de pays de
l'Arde`che). There was also a tennis court, where I had the
chance to play with the man who holds the record for the world's
fastest gate: latency of 12 ps for a multiple-input gate with
fanout > 1. Finally, the relatively limited number of partici-
pants meant that it was easy to ask questions, both during and
after the presentations. It also meant that one could go to (al-
most) all the presentations, and still have time to relax.
The proceedings for the 1994 workshop (and for those held in
1991, 1992 and 1993) can be obtained at a cost of $25 per copy by
contacting:
Nick Kanopoulos
Research Triangle Institute
P. O. Box 12194
Research Triangle Park, NC 27709
TEL: (919)-541-7341
FAX: (919)-541-6515
nick@rti.rti.org
The following is a list of papers presented at the 1994 workshop:
P.1.1 "Rapid Prototyping of a Real-Time Video Encoder" - M. Engels, T.
Meng, Stanford University, Stanford, California, USA.
P.1.2 "Using an FPGA Based Computer as a Hardware Emulator for
Built-In Self-Test Structures" - R.W. Wieler, Z. Zhang, R.D.
McLeod, University of Manitoba, Winnipeg, Manitoba, Canada.
P.1.3 "A Reconfigurable DSP Board Based on Cordic Elements" - E.P.
Mariatos, M.K. Birbas, A.N. Birbas, University of Patras, Patras,
Greece.
P.2.1 "Rapid Prototype of an SIMD Processor Array (using FPGA's)" -
D.L. Andrews, A. Wheeler, University of Arkansas, Fayetteville,
Arkansas, USA; B. Wealand, Lockheed Corporation,
Sunnyvale, California, USA.
P.2.2 "A real-time Test-bed for Prototyping Cell-based Communication
Networks" - C. Papadopoulos, A. Maniatopoulos, T.
Antonakopoulos, V. Makios, University of Patras, Patras, Greece.
P.3.1 "ProTR: A TOOL FOR REAL-TIME SYSTEMS DEVELOPMENT" -
G.D.F. Azevedo, FCTI; H. Azevedo, STC Telecomunicacos; M.
Jino, UNICAMP, Campinas, Spain.
P.3.2 "An Integrated Framework for Rapid System Prototyping and
Automatic Code Distribution" - W. El Kaim, F. Kordon, MASI
Laboratory, Paris, Cedex, France.
P.3.3 "Experience with RAPID Prototypes" - D. Dolev, Hebrew
University, Jerusalem, Israel; R. Strong, E. Wimmers, Almaden
Research Center, San Jose, California, USA.
P.3.4 "An Approach for Hardware-Software Codesign" - T.B. Ismail, M.
Abid, K. O'Brien, A.A. Jerraya, Institut IMAG, Grenoble, Cedex,
France.
P.4.1 "Rapid Development of Signal Processors and the RASSP Program"
- C. Myers, P. Fiore, Lockheed Sanders, Inc., Nashua, New
Hampshire, USA; J.P. Letellier, Naval Research Laboratory,
Washington, DC, USA.
P.4.2 "Geometric Parallelism and Cyclo-Static Data Flow in GRAPE-II" -
R. Lauwereins, P. Wauters, M. Ade, J.A. Peperstraete,
Katholieke Universiteit Leuven, Heverlee, Belgium.
P.4.3 "Buffer Memory Requirements in DSP Applications" - M. Ade, R.
Lauwereins, J.A. Peperstraete, Katholieke Universiteit Leuven,
Heverlee, Belgium.
P.5.1 "Hardware Emulation Board based on FPGAs and Programmable
Interconnections" - O.C.S. Choy, W.Y. Lo, C.F. Chan, The
Chinese University of Hong Kong, Shatin, N.T., Hong Kong.
P.5.2 "Some design issues in Multi-chip FPGA Implementation of DSP
Algorithms" - A. Saha, R. Krishnamurthy, Mississippi State
University, Mississippi State, Mississippi, USA.
P.5.3 "Project Spinnaker: A New Generation of Rapid Prototyping
System" - M. Courtoy, Quickturn Systems, Mountain View,
California, USA.
P.6.1 "Extended VHDL for the Rapid System Prototyping of Systems
With Synthesizable and Nonsynthesizable Subsystems" - J.D.S.
Babcock, A. Dollas, Duke University, Durham, North Carolina,
USA.
P.6.2 "From Behavioral to RTL Models: An Approach" - R. McConnell, D.
Lavenier, Institut de Recherche en Informatique et Systems
Aleatoires, Rennes, Cedex, France.
P.6.3 "Quantitative Design of a Scalable MicroSystem Using ALMA: The
Example of the Dictionary Machine" - J.Y. Brunel, I. Auge, M.
Hervieu, Limeil-Brevannes, Cedex, France.
P.7.1 "Safe Rapid Prototyping of Object-Oriented Database Applications"
- M. Missikoff, M. Toiati, IASI-CNR, Rome, Italy.
P.7.2 "Dynamic Analysis and Replanning Tool (DART): a Case Study of
Accelerated Evolutionary Development" - S.E. Cross, ARPA,
Arlington, Virginia, USA; R. Estrada, BBN Systems and
Technology Corp., Cambridge, Massachusetts, USA.
P.7.3 "A Formal Approach Based on the Rewriting Logic for Prototyping
Distributed Information Systems" - A. Attoui, M. Schneider,
Laboratoire d'Informatique, Aubiere, Cedex, France.
P.8.1 "Algorithms and Architectures to Computational Systems
Implementation" - L. Carro, A. Suzim, Universidade Federal do
Rio Grande do Sul, Porto Alegre, Brazil.
P.8.2 "Accelerating the design process by using architectural synthesis" -
P. Kission, H. Ding, A.A. Jerraya, Laboratory TIMA/INPG,
Grenoble, Cedex, France.
dbouldin@utk.edu
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