MICROELECTRONIC SYSTEMS NEWS



FILENUMBER: 708
BEGIN_KEYWORDS
Procedural CMOS Synthesizer Software
END_KEYWORDS
DATE: july 1994
TITLE: Procedural CMOS Synthesizer Software Available


Procedural CMOS Synthesizer Software Available

(Contributed by Bill Bryan of the Oak Ridge National Lab)

Software is now available to translate  a  netlist  into  a  CMOS
mask-level  description.   As  reported in SunFLASH, Vol 65, #82,
SIDAS, (a Smart IC Design Automation System)  is  now  available.
It  makes  CMOS  layouts  from  netlists  using.  fast procedural
methods (rather than standard cells)  to  generate  the  layouts,
resulting  in  denser layouts. It can handle circuits from one to
10,000 gates.

SIDAS does not use cell libraries, though it can place and  route
hand-crafted  cells.  You can adjust transistor sizes. The system
will automatically split  transistors  larger  than  a  size  you
specify.   Its algorithms include sharing of power wires by adja-
cent gates and other space-saving tricks.

It can place about 2000 transistors in  two  minutes  on  a  SS2.
Designers can edit the resulting placement with a GUI editor, and
pass the modified placement back to the system.  You can also as-
sign priorities to different nets, causing the system to minimize
nets preferentially.

You can locate I/O pin exactly  or  specify  general  constraints
(e.g.,  anywhere  on  the  bottom),  and the system optimizes its
design subject to your specifications.

SIDAS supports both 1 and 2 metal layer (plus poly) routing,  and
uses an over-the-cell routing method if 2 metal layers are avail-
able.

Inputs:
        EDIF 2.0.0 (Gate Level)
        SDL
        GDSII stream file (for hand-crafted cells)

        Technology files (contains design rules)
        Pin Preference files (contains i/o pin  location  prefer-
        ences)
        Equivalence table (describes netlist's instance names)

Outputs:
        GDSII stream
        Spice net list
        SAIFII

Netlist Primitives:
        n-input-NAND, n-input-NOR, n-input-AND, n-input-OR, INV
        Transfer gates (N_TR, P_TR, TR)
        Clocked inverters
        User-defined Complex Gates
        Handcrafted cells

Process customizability includes several files  of  design  rules
and  other  parameters.   You  can,  for  instance, customize the
number of drain contacts or the density of sub-contacts.

SIDAS runs on Sun Sparc machines under  SunOS  4.x.   It  has  an
OpenLook  GUI.   It  needs about 6M disk space and will run under
16M RAM.  It is cpu-speed limited.  It is  licensed  on  per-host
basis.

For more info on SIDAS capabilities, performance, and  licensing,
please contact:

        J.B. Kim, Senior Engineer
        Toppan Electronics
        17310 Redhill Ave
        Suite 350
        Irvine, Ca 92714
        TEL: (714)-863-9240
        FAX: (714)-660-0763
        kim@ele.toppan.com

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