MICROELECTRONIC SYSTEMS NEWS



FILENUMBER: 8018
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Generic Reusable Module FPGA GERM Overhauser Duke
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DATE: november 1994
TITLE: Generic Reusable Module Using FPGAs

Generic Reusable Module Using FPGAs

(Contributed by David Overhauser of Duke Univ.)


The GERM Board for Integrating FPGAs into the 
Entire Digital Design Curriculum

What is the GERM
----------------
   The GEneric Reusable Module (GERM) is a 3"x3.5"(7.6cm x 8.9cm)
Printed Circuit Board (PCB) containing a XILINX 3000 series FPGA and 
associated hardware.  It has been developed to help introduce digital
design using FPGAs into all levels of the undergraduate and graduate
curriculum at Duke University.  The design of the GERM is such that
it is low-cost, stand-alone, and reprogrammable.  It can be configured
as a very low-cost prototyping tool for beginning logic design classes
or be connected with other GERM boards as a tool for implementing
larger digital design projects in advanced and capstone classes.

   When the GERM board is completely populated, nicknamed the Ferrari
model, it contains one XILINX FPGA, a ZIF socket for a standard parallel
EPROM, four 26-pin connectors, and several small components.  This model
of the GERM can be used in a stand-alone mode or connected to a PC or 
workstation through a serial download cable.  In the stand-alone mode
the FPGA program is downloaded from the EPROM.  The connectors can be
used to connect the GERM to laboratory instruments or to other GERM
boards.  Thus, larger designs are possible through the connection of
several GERM boards.  The estimated cost of parts for the Ferrari
configuration is approximately $37, excluding the FPGA and EPROM.
The main hardware costs come from the ZIF socket and connectors.
In addition to the FPGA and EPROM there are very few electronic 
and other components (two LED's, one switch, one header for serial
download, some jumpers. a few resistors and capacitors).

   The minimal GERM configuration, nicknamed the Yugo model, contains
one XILINX FPGA, one 26-pin connector, and several small components.
This model can only be used through a serial download cable.  The
estimated cost of parts for the Yugo configuration is approximately
$8, excluding the FPGA.  Unlike their four wheeled counterparts, the
Yugo models can be turned into Ferraris with the addition of roughly
$30 worth of hardware.

   Parts lists and construction information for populating GERMs can
be found in the GERM User's Guide.  The GERM is designed around a
XILINX XC3030PC-50 or pin compatible FPGA.

Curriculum Usage
----------------
   The GERM has been used as an instructional tool for Introductory
Digital Design courses.  The GERM is used as a lab kit to introduce
students to FPGA technology, reprogrammable hardware, subsystem 
design,
and rapid system prototyping.  The GERM was developed in prototype,
wirewrapped form in 1993, and in small scale production with printed
circuit boards in early 1994.

   GERMs have been used in undergraduate and graduate courses at
Duke University, starting in the Spring Semester of 1994.  The GERM
supplements the current lab kit used in the sophomore level EE151,
Introduction to Switching Theory and Logic Design, and it was also
used in the senior/graduate level EE254, Fault-Tolerant and Testable
Systems.  There are plans to use the GERM also in EE251, Advanced
Digital System Design, and EE261, Introduction to VLSI Design.  
We expect the GERM, its tools, and its design procedures to further
aid the undergraduate and graduate students in the upper level
courses where complex hardware design projects are expected to be
produced in a semester.

Curriculum Tools
----------------
   Tutorials and user's guides have been created which are detailed
enough for both those constructing GERMs and students using GERMs
in digital design laboratories.  Access details are given below.

   GERMs have been used through three design paths: XILINX design
tools, Powerview tools, and Synopsys synthesis tools.  Information
on these design paths is provided in the guides described below.

   Some sample designs laboratory assignments are available in the
1994 International Workshop on Field Programmable Logic (FPL 94) paper
described below.  If necessary, specific files can be provided.

Limitations
-----------
   Although GERMs can be interconnected to form larger designs or used
as routing between designs, the partitioning of the design into each
FPGA is manual.
   Only 18 input/output signals are available on each connector, so
several cables may be required for large designs.
   The GERMs to not have protective circuitry on input/output pads,
therefore care is required when connecting modules.
   The design of the GERM and all material associated with it is
distributed by Duke University free of charge.  The CAD tools that are
needed to design circuits for the GERM (the Xilinx suite and some
schematic entry or language based front end) are not distributed by
Duke and are generally not free of charge.

Additional Information
----------------------
   Several postscript documents about the GERM are available through
anonymous ftp to ee.duke.edu in the directory GERM.  The GERM
User's Guide, which provides GERM construction, usage, and CAD tool
information is in the file GERM_Users_Guide.ps.Z.  A separate guide
for using the GERM with Powerview is in the file
GERM_From_Powerview.ps.Z.  A paper from the September 1994
International Workshop on Field Programmable Logic (FPL 94) in Prague,
including several GERM design examples, is in the file Paper_FPL94.ps.Z.

   Several unpopulated GERM boards have been reserved for distribution
to universities interested in using GERMs in their curriculum.  More
will be fabricated as funds become available.

   For more information about the GERMs or availability of GERM boards,
contact

        Dr. David Overhauser
        Department of Electrical and Computer Engineering
        Duke University
        Box 90291
        Durham, NC  27708
        USA
        + 1 (919) 660-5273
        ovee@ee.duke.edu

        Dr. Apostolos Dollas
        Department of Electronics and Computer Engineering
        Technical University of Crete
        73100 Chania
        GREECE
        + 30 (821) 46-566  Ext. 228
        dollas@ced.tuc.gr