MICROELECTRONIC SYSTEMS NEWS



FILENUMBER: 8023
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text synthesis verilog sternheim
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DATE: november 1994
TITLE: Text on Synthesis using Verilog by Sternheim


Text on Synthesis using Verilog by Sternheim

(Contributed by Michael Ciletti of Univ. of Colorado)

"Digital Design and Synthesis with Verilog HDL" (ISBN  0-9627488-
2-X)  by Sternheim et al.  may be purchased with or without a 32-
bit DOS/PC-based  Verilog  HDL  simulator.  The  text  emphasizes
designing  for synthesis (primarily using Synopsys tools) and the
semantics of the Verilog language.  Each chapter has a full Veri-
log  description of each example discussed in the text, and a set
of useful exercises, mainly for university students.

The text and simulator together costs $100 while the  text  alone
costs $65.  The simulator supports:

		- full Verilog HDL except switch level constructs and 
		  specify blocks.
		- System commands.
		- Verilog-XL compatible command line options.
		- Intel's 386 and upward compatible PC
		- 1 MB RAM
		- 2 MB hard disk
		- A 3 1/2" diskette

The Table of Contents includes:

		Preface
		Why Hardware Description Languages
		Anatomy of the Verilog HDL
		Synthesis Design Method and Verilog for Synthesis, 
		Designing a Pipeline Processor, 
		Building Blocks of a Processor, 
		Designing Cache Memories, 
		Asynchronous I/O: UART, 
		Designing a Floppy Disk Subsystem, 
		Useful Modeling and Debugging Techniques, 
		Condensed Language Reference Manual,
		Formal Syntax definition of Verilog HDL
		Index.

To order, contact:

		Automata Publishing Company,
		1072 S. Saratoga-Sunnyvale Rd.
		#A107
		San Jose, CA 95129
		TEL: (408)-255-0705   
		FAX: (408)-253-7916

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