MICROELECTRONIC SYSTEMS NEWS
FILENUMBER: 9304
BEGIN_KEYWORDS
UDL/I Simulation Synthesis Environment CAD software
END_KEYWORDS
DATE: september 1996
TITLE: UDL/I Simulation/Synthesis Environment
UDL/I Simulation/Synthesis Environment
Unified Design Language for Integrated Circuit (UDL/I) is a
Hardware Description Language (HDL) for logic synthesis.
Since 1990, UDL/I Simulation/Synthesis Environment had been
developed by Japan Electronic Industry Development Association
(JEIDA).
Users of the UDL/I environment can
- simulate behavior of a RTL description in UDL/I
- synthesize a circuit from a RTL description in UDL/I
- simulate behavior of a circuit synthesized
This UDL/I Simulation/Synthesis environment including its source codes
has become open to pulic as a free software and is distributed at WWW .
If you fail to get the distribution package due to slow-data-transfer,
please send E-mail to udli-cad@metsa.astem.or.jp
Best regards,
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ASTEM RI
Micro ElecTronicS Activity division
Kyoto Research Park, 17 Chudoji Minami-machi,
Shimogyo, Kyoto 600 JAPAN
TEL:+81-75-315-8652
FAX:+81-75-315-2898
WWW: ASTEM
udli-cad@metsa.astem.or.jp
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dbouldin@utk.edu