MICROELECTRONIC SYSTEMS NEWS

FILENUMBER: 9816 BEGIN_KEYWORDS SPECIAL_ISSUE DRAM TESTING END_KEYWORDS DATE: July 1998 TITLE: DRAM ARCHITECTURE AND TESTING SPECIAL ISSUE
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IEEE Design and Test of Computers
Theme Issue: DRAM Architecture and Testing

January-March 1999, Volume 16, Number 1

DRAM

IEEE Design and Test of Computers seeks original manuscripts for a
theme issue on architectural and testing aspects of Dynamic Random
Access Memories (DRAMs), scheduled to appear in the first issue of
1999. Articles concerning applied research and practical experience
reports are solicited.  Submitted articles must not have been
previously published or currently submitted for publication elsewhere.
The topics of interest include, but are not limited to:

EMBEDDED MEMORIES

impact, developments, and experiences with embedded macrocells;
reconciling DRAM and logic requirements in a single process;
logic-enhanced DRAMs; processors-in-memories; DRAMs embedded in ASICs;
application-specific DRAMs (graphics, multimedia, communications, ...)

TECHNOLOGY AND STANDARDS

trends in storage cell technology; DRAM-specific processes; circuit
design methodology; fuse technology; packaging; reliability; failure
analysis; high-performance architectures; RAMBUS versus SLDRAM;
impact, developments, and experiences with standards; cache-enhanced
DRAMs

DESIGN

timing system design, timing calibration, synchronous versus
self-timed operation, pipelined design, static and dynamic redundancy,
noise control, error correcting codes, multilevel DRAM, future trends

REPAIR AND TEST

fault models, failure mechanisms, repair algorithms, built-in
self-repair, DRAM test design, design-for-testability, built-in
self-test, parallel test strategies, automatic test equipment, memory
interconnect test

Submit articles by July 24, 1998 to:

Bruce Cockburn, D&T Guest Editor      Phone: 403-492-3827
Electrical and Computer Engineering   Fax: 403-492-1811
238 Civil/Electrical Building         Email: cockburn@ee.ualberta.ca
University of Alberta
Edmonton Alberta, Canada  T6G 2G7

For additional information, consult the web page, contact Dr.
Cockburn, or contact one of the other guest editors:

Fabrizio Lombardi             Fred "Jackie" Meyer
Phone: 409-845-5464           Phone: 409-845-1014
Email: lombardi@cs.tamu.edu   Email: fjmeyer@computer.org

Important dates:

     July 24, 1998:  Submission deadline
September 15, 1998:  Authors notified of acceptance with requested revisions
  October 15, 1998:  Final copy due to Design & Test Managing Editor
January-March 1999:  Publication in IEEE Design and Test of Computers

Submission requirements:

Electronic submission is encouraged; otherwise, send six (6) copies of
the manuscript.  Manuscripts must be in English and not exceed 35
double-spaced pages, inclusive of figures and tables, in A4 or 8.5 by
11 inches.  Type size must be at least 12 point. Each copy of the
manuscript must contain a cover page with author contact information
(name, postal address, telephone number, and e-mail address) and a
100-word abstract.  Manuscripts must be cleared for publication.
Accepted manuscripts will be edited for technical content, structure,
style, clarity, and grammar.


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